1,839 research outputs found
Timing-driven physical design for VLSI circuits using resonant rotary clocking
Paper presented at the Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico.Resonant clocking technologies are next-generation
clocking technologies that provide low or controllable-skew,
low-jitter and multi-gigahertz frequency clock signals with low
power consumption. This paper describes a collection of circuit
partitioning, placement and synchronization methodologies that
enables the implementation of high speed, low power circuits synchronized
with the resonant rotary clocking technology. Resonant
rotary clocking technology inherently supports (and requires)
non-zero clock skew operation, which permits further improved
circuit performances. The proposed physical design flow entails
integrated circuit partitioning and placement methodologies that
permit the hierarchical application of non-zero clock skew system
timing. This design flow is shown to be a computationally efficient
implementation method
Recommended from our members
Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications
High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator
Advanced Timing and Synchronization Methodologies for Digital VLSI Integrated Circuits
This dissertation addresses timing and synchronization methodologies that are critical to the design, analysis and optimization of high-performance, integrated digital VLSI systems. As process sizes shrink and design complexities increase, achieving timing closure for digital VLSI circuits becomes a significant bottleneck in the integrated circuit design flow. Circuit designers are motivated to investigate and employ alternative methods to satisfy the timing and physical design performance targets. Such novel methods for the timing and synchronization of complex circuitry are developed in this dissertation and analyzed for performance and applicability.Mainstream integrated circuit design flow is normally tuned for zero clock skew, edge-triggered circuit design. Non-zero clock skew or multi-phase clock synchronization is seldom used because the lack of design automation tools increases the length and cost of the design cycle. For similar reasons, level-sensitive registers have not become an industry standard despite their superior size, speed and power consumption characteristics compared to conventional edge-triggered flip-flops.In this dissertation, novel design and analysis techniques that fully automate the design and analysis of non-zero clock skew circuits are presented. Clock skew scheduling of both edge-triggered and level-sensitive circuits are investigated in order to exploit maximum circuit performances. The effects of multi-phase clocking on non-zero clock skew, level-sensitive circuits are investigated leading to advanced synchronization methodologies. Improvements in the scalability of the computational timing analysis process with clock skew scheduling are explored through partitioning and parallelization.The integration of the proposed design and analysis methods to the physical design flow of integrated circuits synchronized with a next-generation clocking technology-resonant rotary clocking technology-is also presented. Based on the design and analysis methods presented in this dissertation, a computer-aided design tool for the design of rotary clock synchronized integrated circuits is developed
Low Power Resonant Rotary Global Clock Distribution Network Design
Along with the increasing complexity of the modern very large scale integrated (VLSI) circuit design, the power consumption of the clock distribution network in digital integrated circuits is continuously increasing. In terms of power and clock skew, the resonant clock distribution network has been studied as a promising alternative to the conventional clock distribution network. Resonant clock distribution network, which works based on adiabatic switching principles, provides a complete solution for on-chip clock generation and distribution for low-power and low-skew clock network designs for high-performance synchronous VLSI circuits.This dissertation work aims to develop the global clock distribution network for one kind of resonant clocking technologies: The resonant rotary clocking technology. The following critical aspects are addressed in this work: (1) A novel rotary oscillator array (ROA) topology is proposed to solve the signal rotation direction uniformity problem, in order to support the design of resonant rotary clocking based low-skew clock distribution network; (2) A synchronization scheme is proposed to solve the large scale rotary clocking generation circuit synchronization problem; (3) A low-skew rotary clock distribution network design methodology is proposed with frequency, power and skew optimizations; (4) A resonant rotary clocking based physical design flow is proposed, which can be integrated in the current mainstream IC design flow; (5) A dynamic rotary frequency divider is proposed for dynamic frequency scaling applications. Experimental and theoretical results show: (1) The efficiency of the proposed methodology in the construction of low-skew, low-power resonant rotary clock distribution network. (2) The effectiveness of the dynamic rotary frequency divider in extending the operating frequency range of the low-power resonant rotary based applications.Ph.D., Electrical Engineering -- Drexel University, 201
Distributed synchronization algorithms for wireless sensor networks
The ability to distribute time and frequency among a large population of interacting agents is of interest for diverse disciplines, inasmuch as it enables to carry out complex cooperative tasks. In a wireless sensor network (WSN), time/frequency synchronization allows the implementation of distributed signal processing and coding techniques, and the realization of coordinated access to the shared wireless medium. Large multi-hop WSN\u27s constitute a new regime for network synchronization, as they call for the development of scalable, fully distributed synchronization algorithms. While most of previous research focused on synchronization at the application layer, this thesis considers synchronization at the lowest layers of the communication protocol stack of a WSN, namely the physical and the medium access control (MAC) layer. At the physical layer, the focus is on the compensation of carrier frequency offsets (CFO), while time synchronization is studied for application at the MAC layer. In both cases, the problem of realizing network-wide synchronization is approached by employing distributed clock control algorithms based on the classical concept of coupled phase and frequency locked loops (PLL and FLL). The analysis takes into account communication, signaling and energy consumption constraints arising in the novel context of multi-hop WSN\u27s. In particular, the robustness of the algorithms is checked against packet collision events, infrequent sync updates, and errors introduced by different noise sources, such as transmission delays and clock frequency instabilities. By observing that WSN\u27s allow for greater flexibility in the design of the synchronization network architecture, this work examines also the relative merits of both peer-to-peer (mutually coupled - MC) and hierarchical (master-slave - MS) architectures. With both MC and MS architectures, synchronization accuracy degrades smoothly with the network size, provided that loop parameters are conveniently chosen. In particular, MS topologies guarantee faster synchronization, but they are hindered by higher noise accumulation, while MC topologies allow for an almost uniform error distribution at the price of much slower convergence. For all the considered cases, synchronization algorithms based on adaptive PLL and FLL designs are shown to provide robust and scalable network-wide time and frequency distribution in a WSN
NASA patent abstracts bibliography: A continuing bibliography. Section 1: Abstracts (supplement 38)
Abstracts are provided for 132 patents and patent applications entered into the NASA scientific and technical information system during the period July 1990 through December 1990. Each entry consists of a citation, an abstract, and in most cases, a key illustration selected from the patent or patent application
Coherent Resonant Properties of Cardiac Cells
Materials / States of matte
- …