Software Defined Radio Platform for Cognitive Radio: Design and Hierarchical Management

ISBN 978-953-307-274-6Cognitive radio (CR) and/or Software Defined Radio (SDR) inherently require multiband and multi-standard wireless circuit. A SDR is a communications device whose functionality is defined in software. Defining the radio behaviour in software removes the need for hardware alterations during a technology upgrade. A promised open architecture platform for SDR is proposed in this chapter. The platform consists of reconfigurable and reprogrammable hardware platform which provide different standards with a common platform, the SDR software framework which control and manage the whole systems, and the protocol processing software modules which is built on reusable protocol libraries. The main idea here is to have a very flexible platform that enables us to test the validity of the following design approaches: FPGA dynamic partial reconfiguration techniques, parameterization design approach using common operators, hierarchical distributed reconfiguration management

Exploiting partial reconfiguration through PCIe for a microphone array network emulator

The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization. However, the evaluation and the selection of the most accurate and power-efficient network’s topology are not trivial when considering dynamic MEMS microphone arrays. Although software simulators are usually considered, they consist of high-computational intensive tasks, which require hours to days to be completed. In this paper, we present an FPGA-based platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network’s topology, or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. The platform is designed to exploit the FPGA’s partial reconfiguration feature to increase the flexibility of the network emulator as well as to increase performance thanks to the use of the PCI-express high-bandwidth interface. On the one hand, the network emulator presents a higher flexibility by partially reconfiguring the nodes’ architecture in runtime. On the other hand, a set of strategies and heuristics to properly use partial reconfiguration allows the acceleration of the emulation by exploiting the execution parallelism. Several experiments are presented to demonstrate some of the capabilities of our platform and the benefits of using partial reconfiguration

Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-On-Chip

We have previously argued the benefits of embedded Linux as an operating system platform for reconfigurable system-on-chip design. In this paper we describe our approach to building tools for the implementation of dynamically and self-reconfigurable systems, and show that embedded Linux is a natural and powerful platform on which to build these tools. We present examples and demonstrations that show how complex operations such as obtaining partial bit streams from remote servers and initiating reconfiguration are achieved with a single line of Linux shell script

FPGA dynamic and partial reconfiguration : a survey of architectures, methods, and applications

Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption

From a Configuration Management to a Cognitive Radio Management of SDR Systems

International audienceThis paper proposes a functional management architecture for Cognitive Radio systems. It relies on a previously defined configuration management architecture for multi-standard SDR systems, and complement it to support cognitive radio features. This paper explains the requirements of Cognitive Radio systems in terms of reconfiguration, smartness and sensing capabilities. A configuration management architecture capable of dealing with the hardware heterogeneity and a wide range of reconfiguration scenarios expected with SDR systems is presented. The management is distributed over the system and a hierarchical dependency is set on 3 layers, each having a different level of knowledge of the system and the associated hardware constraints of the elements it supervises. Then a cognitive management functional architecture is derived from the previous one, copying the 3 layers of hierarchy. The roles of the elements of each layer are discussed, as well as their respective interactions and their relationships with the elements of the configuration management architecture