Distributed implementation of Grafcets through IEC 61499

Comunicación presentada en 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), 2020A Grafcet is a standardized model for describing the behavior of systems which is popular among automation engineers. As the Grafcet standard excludes implementation details, the models are typically translated to automation software. Such software was traditionally programmed in one of the languages specified in IEC 61131-3. Nowadays, automation software is increasingly modelled in IEC 61499 which facilitates designing distributed control systems. In this paper, we define a standardized translation methodology, so that automation engineers can benefit from the advantages of IEC 61499 while continuing to use Grafcet. We discuss the differences between Grafcet and IEC 61499. We translated a Grafcet model into an IEC 61499 application to illustrate the process and derive guidelines for application designers. For the core concepts of Grafcet, we present the corresponding structure in IEC 61499

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed

The LifeV library: engineering mathematics beyond the proof of concept

LifeV is a library for the finite element (FE) solution of partial differential equations in one, two, and three dimensions. It is written in C++ and designed to run on diverse parallel architectures, including cloud and high performance computing facilities. In spite of its academic research nature, meaning a library for the development and testing of new methods, one distinguishing feature of LifeV is its use on real world problems and it is intended to provide a tool for many engineering applications. It has been actually used in computational hemodynamics, including cardiac mechanics and fluid-structure interaction problems, in porous media, ice sheets dynamics for both forward and inverse problems. In this paper we give a short overview of the features of LifeV and its coding paradigms on simple problems. The main focus is on the parallel environment which is mainly driven by domain decomposition methods and based on external libraries such as MPI, the Trilinos project, HDF5 and ParMetis. Dedicated to the memory of Fausto Saleri.Comment: Review of the LifeV Finite Element librar

On the automated compilation of UML notation to a VLIW chip multiprocessor

With the availability of more and more cores within architectures the process of extracting implicit and explicit parallelism in applications to fully utilise these cores is becoming complex. Implicit parallelism extraction is performed through the inclusion of intelligent software and hardware sections of tool chains although these reach their theoretical limit rather quickly. Due to this the concept of a method of allowing explicit parallelism to be performed as fast a possible has been investigated. This method enables application developers to perform creation and synchronisation of parallel sections of an application at a finer-grained level than previously possible, resulting in smaller sections of code being executed in parallel while still reducing overall execution time. Alongside explicit parallelism, a concept of high level design of applications destined for multicore systems was also investigated. As systems are getting larger it is becoming more difficult to design and track the full life-cycle of development. One method used to ease this process is to use a graphical design process to visualise the high level designs of such systems. One drawback in graphical design is the explicit nature in which systems are required to be generated, this was investigated, and using concepts already in use in text based programming languages, the generation of platform-independent models which are able to be specialised to multiple hardware architectures was developed. The explicit parallelism was performed using hardware elements to perform thread management, this resulted in speed ups of over 13 times when compared to threading libraries executed in software on commercially available processors. This allowed applications with large data dependent sections to be parallelised in small sections within the code resulting in a decrease of overall execution time. The modelling concepts resulted in the saving of between 40-50% of the time and effort required to generate platform-specific models while only incurring an overhead of up to 15% the execution cycles of these models designed for specific architectures

MARTE based design flow for Partially Reconfigurable Systems-on-Chips

International audienceSystems-on-Chip (SoCs) are considered an integral solution for designing embedded systems, for targeting complex intensive parallel computation applications. As advances in SoC technology permit integration of increasing number of hardware resources on a single chip, the targeted application domains such as software-defined radio are become increasingly sophisticated. The fallout of this complexity is that the system design, particularly software design, does not evolve at the same pace as that of hardware leading to a significant productivity gap. Adaptivity and reconfigurability are also critical issues for SoCs which must be able to cope with end user environment and requirements