NoC-based Architectures for Real-Time Applications : Performance Analysis and Design Space Exploration

Monoprocessor architectures have reached their limits in regard to the computing power they offer vs the needs of modern systems. Although multicore architectures partially mitigate this limitation and are commonly used nowadays, they usually rely on intrinsically non-scalable buses to interconnect the cores. The manycore paradigm was proposed to tackle the scalability issue of bus-based multicore processors. It can scale up to hundreds of processing elements (PEs) on a single chip, by organizing them into computing tiles (holding one or several PEs). Intercore communication is usually done using a Network-on-Chip (NoC) that consists of interconnected onchip routers allowing communication between tiles. However, manycore architectures raise numerous challenges, particularly for real-time applications. First, NoC-based communication tends to generate complex blocking patterns when congestion occurs, which complicates the analysis, since computing accurate worst-case delays becomes difficult. Second, running many applications on large Systems-on-Chip such as manycore architectures makes system design particularly crucial and complex. On one hand, it complicates Design Space Exploration, as it multiplies the implementation alternatives that will guarantee the desired functionalities. On the other hand, once a hardware architecture is chosen, mapping the tasks of all applications on the platform is a hard problem, and finding an optimal solution in a reasonable amount of time is not always possible. Therefore, our first contributions address the need for computing tight worst-case delay bounds in wormhole NoCs. We first propose a buffer-aware worst-case timing analysis (BATA) to derive upper bounds on the worst-case end-to-end delays of constant-bit rate data flows transmitted over a NoC on a manycore architecture. We then extend BATA to cover a wider range of traffic types, including bursty traffic flows, and heterogeneous architectures. The introduced method is called G-BATA for Graph-based BATA. In addition to covering a wider range of assumptions, G-BATA improves the computation time; thus increases the scalability of the method. In a second part, we develop a method addressing design and mapping for applications with real-time constraints on manycore platforms. It combines model-based engineering tools (TTool) and simulation with our analytical verification technique (G-BATA) and tools (WoPANets) to provide an efficient design space exploration framework. Finally, we validate our contributions on (a) a serie of experiments on a physical platform and (b) two case studies taken from the real world: an autonomous vehicle control application, and a 5G signal decoder applicatio

Real-Time Guarantees in Routerless Networks-on-Chip

This paper considers the use of routerless networks-on-chip as an alternative on-chip interconnect for multiprocessor systems requiring hard real-time guarantees for inter-processor communication. It presents a novel analytical framework that can provide latency upper bounds to real-time packet flows sent over routerless networks-on-chip, and it uses that framework to evaluate the ability of such networks to provide real-time guarantees. Extensive comparative analysis is provided, considering different architectures for routerless networks and a state-of-the-art wormhole network based on priority-preemptive routers as a baseline

Deployment and Debugging of Real-Time Applications on Multicore Architectures

It is essential to enable information extraction from software. Program tracing techniques are an example of information extraction. Program tracing extracts information from the program during execution. Tracing helps with the testing and validation of software to ensure that the software under test is correct. Information extraction is done by instrumenting the program. Logged information can be stored in dedicated logging memories or can be buffered and streamed off-chip to an external monitor. The designer inspects the trace after execution to identify potentially erroneous state information. In addition, the trace can provide the state information that serves as input to generate the erroneous output for reproducibility. Information extraction can be difficult and expensive due to the increase in size and complexity of modern software systems. For the sub-class of software systems known as real-time systems, these issues are further aggravated. This is because real-time systems demand timing guarantees in addition to functional correctness. Consequently, any instrumentation to the original program code for the purpose of information extraction may affect the temporal behaviors of the program. This perturbation of temporal behaviors can lead to the violation of timing constraints, which may bias the program execution and/or cause the program to miss its deadline. As a result, there is considerable interest in devising techniques to allow for information extraction without missing a program’s deadline that is known as time-aware instrumentation. This thesis investigates time-aware instrumentation mechanisms to instrument programs while respecting their timing constraints and functional behavior. Knowledge of the underlying hardware on which the software runs, enables the extraction of more information via the instrumentation process. Chip-multiprocessors offer a solution to the performance bottleneck on uni-processors. Providing timing guarantees for hard real-time systems, however, on chip-multiprocessors is difficult. This is because conventional communication interconnects are designed to optimize the average-case performance. Therefore, researchers propose interconnects such as the priority-aware networks to satisfy the requirements of hard real-time systems. The priority-aware interconnects, however, lack the proper analysis techniques to facilitate the deployment of real-time systems. This thesis also investigates latency and buffer space analysis techniques for pipelined communication resource models, as well as algorithms for the proper deployment of real-time applications to these platforms. The analysis techniques proposed in this thesis provide guarantees on the schedulability of real-time systems on chip-multiprocessors. These guarantees are based on reducing contention in the interconnect while simultaneously accurately computing the worst-case communication latencies. While these worst-case latencies provide bounds for computing the overall worst-case execution time of applications on chip-multiprocessors, they also provide means to assigning instrumentation budgets required by time-aware instrumentation. Leveraging these platform-specific analysis techniques for the assignment of instrumentation budgets, allows for extracting more information from the instrumentation process

Performance Analysis in IP-Based Industrial Communication Networks

S rostoucím počtem řídicích systémů a jejich distribuovanosti získávájí komunikační sítě na důležitosti a objevují se nové výzkumné trendy. Hlavní problematikou v této oblasti, narozdíl od dřívějších řídicích systémů využívajících dedikovaných komunikačních obvodů, je časově proměnné zpoždění měřicích a řídicích signálů způsobené paketově orientovanými komunikačními prostředky, jako např. Ethernet. Aspekty komunikace v reálném čase byly v těchto sítích již úspěšně vyřešeny. Nicméně, analýzy trendů trhu předpovídají budoucí využití také IP sítí v průmyslové komunikaci pro časově kritickou procesní vyměnu dat. IP komunikace má ovšem pouze omezenou podporu v instrumentaci pro průmyslovou automatizace. Tato výzva byla nedávno technicky vyřešena v rámci projektu Virtual Automation Networks (virtuální automatizační sítě - VAN) zapojením mechanismů kvality služeb (QoS), které jsou schopny zajistit měkkou úroveň komunikace v reálném čase. Předložená dizertační práce se zaměřuje na aspekty výkonnosti reálného času z analytického hlediska a nabízí prostředek pro hodnocení využitelnosti IP komunikace pro budoucí průmyslové aplikace. Hlavním cílem této dizertační práce je vytvoření vhodného modelovacího rámce založeného na network calculus, který pomůže provést worst-case výkonnostní analýzu časového chování IP komunikačních sítí a jejich prvků určených pro budoucí použití v průmyslové automatizaci. V práci byla použita empirická analýza pro určení dominantních faktorů ovlivňujících časového chování síťových zařízení a identifikaci parametrů modelů těchto zařízení. Empirická analýza využívá nástroj TestQoS vyvinutý pro tyto účely. Byla navržena drobná rozšíření rámce network calculus, která byla nutná pro modelování časového chování používaných zařízení. Bylo vytvořeno několik typových modelů zařízení jako výsledek klasifikace různých architektur síťových zařízení a empiricky zjištěných dominantních faktorů. U modelovaných zařízení byla využita nová metoda identifikace parametrů. Práce je zakončena validací časových modelů dvou síťových zařízení (přepínače a směrovače) oproti empirickým pozorováním.With the growing scale of control systems and their distributed nature, communication networks have been gaining importance and new research challenges have been appearing. The major problem, contrary to previously used control systems with dedicated communication circuits, is time-varying delay of control and measurement signals introduced by packet-switched networks, such as Ethernet. The real-time issues in these networks have been tackled by proper adaptations. Nevertheless, market trend analyses foresee also future adoptions of IP-based communication networks in industrial automation for time-critical run-time data exchange. IP-based communication has only a limited support from the existing instrumentation in industrial automation. This challenge has recently been technically tackled within the Virtual Automation Networks (VAN) project by adopting the quality of service (QoS) architecture delivering soft-real-time communication behaviour. This dissertation focuses on the real-time performance aspects from the analytical point of view and provides means for applicability assessment of IP-based communication for future industrial applications. The main objective of this dissertation is establishment of a relevant modelling framework based on network calculus which will assist worst-case performance analysis of temporal behaviour of IP-based communication networks and networking devices intended for future use in industrial automation. Empirical analysis was used to identify dominant factors influencing the temporal performance of networking devices and for model parameter identification. The empirical analysis makes use of the TestQoS tool developed for this purpose. Minor extensions to the network calculus framework were proposed enabling to model the required temporal behaviour of networking devices. Several exemplary models were inferred as a result of classification of different networking device architectures and empirically identified dominant factors. A novel method for parameter identification was used with the modelled devices. Finally, two temporal models of networking devices (a switch and a router) were validated against empirical observations.

Power-aware systems

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 147-156).In this thesis, we formalize the notion of power-aware systems and present a methodology to systematically enhance power-awareness. We define a power-aware system as one which scales its power consumption with changes in its operating scenario with a view to maximizing its energy efficiency. Operating scenarios are primarily characterized by five dimensions - input statistics, output quality requirements, tolerable latency (and/or throughput constraints), internal state and environmental conditions. We quantify the power-awareness of a system by equating it to the energy efficiency with which it can track changes along these dimensions. This is done by comparing the system's energy consumption in a scenario to that of a dedicated system constructed to execute only that scenario as energy efficiently as possible. We then propose a systematic technique that enhances the power-awareness of a system by composing ensembles of point systems. This technique is applied to multipliers, register-files, digital filters and variable-voltage processors demonstrating increases in battery-lifetimes of 60%-200%. In the second half of this thesis we apply power-awareness concepts to data-gathering wireless networks. We derive fundamental bounds on the lifetime of networks and demonstrate the tightness of these bounds using a combination of analytical arguments and simulation. Finally, we show that achieving a high degree of power-awareness in a wireless sensor network is equivalent to optimally or near-optimally solving the role-assignment problem. Provably optimal role assignment strategies using linear programming are presented. Hence, optimal strategies can be determined in a time that is polynomial in the number of nodes. As a result of applying power-awareness formalisms, the energy efficiency, and hence the lifetime of data gathering networks increases significantly over power-unaware schemes.by Manish Bhardwaj.S.M

Detection, Receivers, and Performance of CPFSK and CPCK

Continuous Phase Modulation (CPM) is a power/bandwidth efficient signaling technique for data transmission. In this thesis, two subclasses of this modulation called Continuous Phase Frequency Shift Keying (CPFSK) and Continuous Phase Chirp Keying (CPCK) are considered and their descriptions and properties are discussed in detail and several illustrations are given. Bayesian Maximum Likelihood Ratio Test (MLRT) is designed for detection of CPFSK and CPCK in AWGN channel. Based on this test, an optimum receiver structure, that minimizes the total probability of error, is obtained. Using high- and low-SNR approximations in the Bayesian test, two receivers, whose performances are analytically easy-to-evaluate relative to the optimum receiver, are identified. Next, a Maximum Likelihood Sequence Detection (MLSD) technique for CPFSK and CPCK is considered and a simplified and easy-to-understand structure of the receiver is presented. Finally, a novel Decision Aided Receiver (DAR) for detection of CPFSK and CPCK is presented and closed-form expressions for its Bits Error Rate (BER) performance are derived. Throughout the thesis, performances of the receivers are presented in terms of probability of error as a function of Signal-to-Noise Ratio (SNR), modulation parameters and number of observation intervals of the received waveform. Analytical results wherever possible and, in general, simulation results are presented. An analysis of numerical results is given from the viewpoint of the ability of CPFSK and CPCK to operate over AWGN Channel

Power, Energy, and Thermal Management for Clustered Manycores

Efficient and effective system-level power, energy, and thermal management are very important issues in modern computing systems, for which clustered architectures with multiple voltage islands are an expected compromise between global and per-core DVFS. In this dissertation, we focus on two of the most relevant problems for such architectures, specifically, optimizing performance under power/thermal constraints, and minimizing energy under performance constraints

Consistency techniques in constraint networks

Ph.DDOCTOR OF PHILOSOPH