Study of a signal processor employing a synthetic phase isolator

Evaluation of signal data processor employing synthetic phase isolator techniqu

Analysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologies

Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters. In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process. This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms. The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time. Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB

Modulation transfer functions of A.C. servomechanism components

Imperial Users onl

Optical frequency comb technology for ultra-broadband radio-frequency photonics

The outstanding phase-noise performance of optical frequency combs has led to a revolution in optical synthesis and metrology, covering a myriad of applications, from molecular spectroscopy to laser ranging and optical communications. However, the ideal characteristics of an optical frequency comb are application dependent. In this review, the different techniques for the generation and processing of high-repetition-rate (>10 GHz) optical frequency combs with technologies compatible with optical communication equipment are covered. Particular emphasis is put on the benefits and prospects of this technology in the general field of radio-frequency photonics, including applications in high-performance microwave photonic filtering, ultra-broadband coherent communications, and radio-frequency arbitrary waveform generation.Comment: to appear in Laser and Photonics Review

Energy-Efficient Digital Signal Processing for Fiber-Optic Communication Systems

Modern fiber-optic communication systems rely on complex digital signal processing (DSP) and forward error correction (FEC), which contribute to a significant amount of the over-all link power dissipation. Bandwidth demands are evergrowing and circuit technology scaling will due to fundamental reasons come to an end; energy-efficient design of DSP is thus necessary both from a sustainability perspective and a technical perspective. This thesis explores energy-efficient design of the sub-systems that are estimated to contribute to the majority of the receiver application-specific integrated-circuit power dissipation: chromatic-dispersion compensation, dynamic equalization, nonlinearity mitigation, and forward error correction. With a focus on real-time-processing circuit implementation of the considered algorithms, aspects such as finite-precision effects, pipelining, and parallel processing are explored, the impact on compensation and correction performance is investigated, and energy-efficient circuit implementations are developed. The sub-systems are investigated both individually, and in a system context. DSP designs showing significant energy-efficiency improvements are presented, as well as very high-throughput, energy-efficient, FEC designs. The subsystems are also considered in the context of datacenter interconnect links, and it is shown that DSP-based coherent systems are feasible even in power constrained settings

A 1.06 micrometer avalanche photodiode receiver

The development of a complete solid state 1.06 micron optical receiver which can be used in optical communications at data rates approaching 1.5 Gb/s, or in other applications requiring sensitive, short pulse detection, is reported. This work entailed both the development of a new type of heterojunction III-V semiconductor alloy avalanche photodiode and an extremely charge-sensitive wideband low noise preamp design making use of GaAs Schottky barrier-gate field effect transistors (GAASFET's) operating in in the negative-feedback transimpedance mode. The electrical characteristics of the device are described

The 1.06 micrometer avalanche photodiode detectors with integrated circuit preamplifiers

The development of a complete solid state 1.06 micron optical receiver which can be used in optical communications at data rates approaching 1.5 Gb/s, or in other applications requiring sensitive, short-pulse detection, is reported. This work entailed both the development of a new type of heterojunction 3-5 semiconductor alloy avalanche photodiode and an extremely charge-sensitive wideband low-noise preamp design making use of GaAs Schottky barrier-gate field effect transistors