異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

US Microelectronics Packaging Ecosystem: Challenges and Opportunities

The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technological solutions to enhance cost-effectiveness while incorporating more features into the silicon footprint. One promising approach is Heterogeneous Integration (HI), which involves advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, adopting HI introduces design and security challenges. To enable HI, research and development of advanced packaging is crucial. The existing research raises the possible security threats in the advanced packaging supply chain, as most of the Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors are offshore. To deal with the increasing demand for semiconductors and to ensure a secure semiconductor supply chain, there are sizable efforts from the United States (US) government to bring semiconductor fabrication facilities onshore. However, the US-based advanced packaging capabilities must also be ramped up to fully realize the vision of establishing a secure, efficient, resilient semiconductor supply chain. Our effort was motivated to identify the possible bottlenecks and weak links in the advanced packaging supply chain based in the US.Comment: 22 pages, 8 figure

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Laser-driven micro-transfer printing for MEMS/NEMS integration

Heterogeneous materials integration, motivated by material transfer processes, has evolved to address the technology gap between the conventional micro-fabrication processes and multi-layer functional device integration. In its basic embodiment, micro-transfer printing is used to deterministically transfer and micro-assemble prefabricated microstructures/devices, referred to as “ink,” from donor substrates to receiving substrates using a viscoelastic elastomer stamp, usually made out of polydimethylsiloxane (PDMS). Thin-film release is, in general, difficult to achieve at the micro-scale (surface effects dominate). However, it becomes dependent on the receiving substrate’s properties and preparation. Laser Micro-Transfer Printing (LMTP) is a laser-driven version of the micro-transfer printing process that enables non-contact release of the microstructure by inducing a mismatch thermal strain at the ink-stamp interface; making the transfer printing process independent from the properties or preparation of the receiving substrate. In this work, extensive studies are conducted to characterize, model, predict, and improve the capabilities of the LMTP process in developing a robust non-contact pattern transfer process. Using micro-fabricated square silicon inks and varying the lateral dimensions and thickness of the ink, the laser pulse duration required to drive the delamination, referred to as “delamination time,” is experimentally observed using high-speed camera recordings of the delamination process for different laser beam powers. The power absorbed by the ink is measured to estimate the total energy stored in the ink-stamp system and available to initiate and propagate the delamination crack at the interface. These experiments are used as inputs for an opto-thermo-mechanical model to understand how the laser energy is converted to thermally-induced stresses at the ink-stamp interface to release the inks. The modeling approach is based on first developing an analytical optical absorption model, based on Beer-Lambert law, under the assumption that optical absorption during the LMTP process is decoupled from thermo-mechanical physics. The optical absorption model is used to estimate the heating rate of the ink-stamp system during the LMTP process that, in turn, is used as an input to the coupled thermo-mechanical Finite Element Analysis (FEA) model. Fracture mechanics quantities such as the Energy Release Rate (ERR) and the Stress Intensity Factors (SIFs) are estimated using the model. Then, the thermal stresses at the crack tip, evaluated by the SIFs, are decomposed into two components based on originating causes: CTE mismatch between the ink and the stamp, and thermal gradient within the PDMS stamp. Both the delamination time from the high-speed camera experiments and thermo-mechanical FEA model predictions are used to understand and improve the process’s performance under different printing conditions. Several studies are conducted to understand the effect of other process parameters such as the dimensions and materials of the stamp, the ink-stamp alignment, and the transferred silicon ink shape on the process performance and mechanism. With an objective of reducing the delamination time, the delamination energy, and the temperature of the ink-stamp interface during printing, different patterned stamp designs (cavity, preloading, and thin-walls) have been proposed. Cavity, preloading, and thin-wall stamps are designed to generate thermally-induced air pressure at the ink-stamp interface, to store strain energy at the interface, and to generate thermally-induced air pressure at the preloaded interface, respectively. Cohesive Zone Modeling (CZM) based models are developed to estimate the equilibrium solution of the collapsed patterned stamp after the ink pick-up process, and to evaluate the patterned stamps’ performance during the LMTP process. The patterned stamps show significant improvements in delamination times and delamination energies (up to 35%) and acceptable improvement of the interface temperature at the delamination point (up to 16%) for given printing conditions

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

三次元集積回路におけるチップ間ノイズ結合のその場評価と解析手法に関する研究

博士（工学）神戸大