3,367 research outputs found

    Stored state asynchronous sequential circuits

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    Journal ArticleA method is described for realizing asynchronous sequential circuits in a manner analogous to the stored state method for synchronous sequential circuits. the method simplifies the process of constructing asynchronous sequential circuits, allows utilization of existing MSI parts, and avoids the necessity for concern with races or hazards

    Asynchronous sequential circuit design using pass transistor iterative logic arrays

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    The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations

    Synthesis of multiple-input change asynchronous finite state machines

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    Asynchronous finite state machines (AFSMS) have been limited because multiple-input changes have been disallowed. In this paper, we present an architecture and synthesis system to overcome this limitation. The AFSM marks potentially hazardous state transitions, and prevents output during them. A synthesis tool to create the AFS M incorporates novel algorithms to detect the hazardous states

    Hierarchical gate-level verification of speed-independent circuits

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    This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.Peer ReviewedPostprint (published version

    Asynchronous techniques for system-on-chip design

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    SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

    Exact Essential-Hazard-Free State Minimization of Incompletely Specified Asynchronous Sequential Machines

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    To insure correct dynamic behaviour of asynchronous sequential machines, hazards must be eliminated for they may cause malfunctions of the whole system. However, Hazard-free state minimization has received almost no prior attention in the literature. This paper describes an exact algorithm for essential-hazard-free state minimization of incompletely specified asynchronous sequential machines. Novel techniques for the elimination of apparent and potential essential hazards are proposed and exploited in our algorithm. The algorithm has been implemented and applied to over a dozen asynchronous sequential machines. Results are compared with results of non-essential-hazard-free method SIS. Most of the tested cases can be reduced to essential hazard free flow tables

    A DESIGN METHOD OF ASYNCHRONOUS SEQUENTIAL CIRCUITS BASED ON FLOW DIAGRAM

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    A systematic, asynchronous design method based on a flow diagram is shown. The realization utilizes a so-called phase-register coded 1 out of n. A phase consists of so-called phase- register cells, which are elementary asynchronous networks including edge-sensitive integrated circuit flip-flops. The circuits developed by the proposed method are free of critical races and essential hazard faults

    Design of an asynchronous processor

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