87 research outputs found
Decomposition Methods for Large Scale LP Decoding
When binary linear error-correcting codes are used over symmetric channels, a
relaxed version of the maximum likelihood decoding problem can be stated as a
linear program (LP). This LP decoder can be used to decode error-correcting
codes at bit-error-rates comparable to state-of-the-art belief propagation (BP)
decoders, but with significantly stronger theoretical guarantees. However, LP
decoding when implemented with standard LP solvers does not easily scale to the
block lengths of modern error correcting codes. In this paper we draw on
decomposition methods from optimization theory, specifically the Alternating
Directions Method of Multipliers (ADMM), to develop efficient distributed
algorithms for LP decoding.
The key enabling technical result is a "two-slice" characterization of the
geometry of the parity polytope, which is the convex hull of all codewords of a
single parity check code. This new characterization simplifies the
representation of points in the polytope. Using this simplification, we develop
an efficient algorithm for Euclidean norm projection onto the parity polytope.
This projection is required by ADMM and allows us to use LP decoding, with all
its theoretical guarantees, to decode large-scale error correcting codes
efficiently.
We present numerical results for LDPC codes of lengths more than 1000. The
waterfall region of LP decoding is seen to initiate at a slightly higher
signal-to-noise ratio than for sum-product BP, however an error floor is not
observed for LP decoding, which is not the case for BP. Our implementation of
LP decoding using ADMM executes as fast as our baseline sum-product BP decoder,
is fully parallelizable, and can be seen to implement a type of message-passing
with a particularly simple schedule.Comment: 35 pages, 11 figures. An early version of this work appeared at the
49th Annual Allerton Conference, September 2011. This version to appear in
IEEE Transactions on Information Theor
Hardware Based Projection onto The Parity Polytope and Probability Simplex
This paper is concerned with the adaptation to hardware of methods for
Euclidean norm projections onto the parity polytope and probability simplex. We
first refine recent efforts to develop efficient methods of projection onto the
parity polytope. Our resulting algorithm can be configured to have either
average computational complexity or worst case
complexity on a serial processor where
is the dimension of projection space. We show how to adapt our projection
routine to hardware. Our projection method uses a sub-routine that involves
another Euclidean projection; onto the probability simplex. We therefore
explain how to adapt to hardware a well know simplex projection algorithm. The
hardware implementations of both projection algorithms achieve area scalings of
at a delay of
. Finally, we present numerical results in
which we evaluate the fixed-point accuracy and resource scaling of these
algorithms when targeting a modern FPGA
Gradient Flow Decoding for LDPC Codes
The power consumption of the integrated circuit is becoming a significant
burden, particularly for large-scale signal processing tasks requiring high
throughput. The decoding process of LDPC codes is such a heavy signal
processing task that demands power efficiency and higher decoding throughput. A
promising approach to reducing both power and latency of a decoding process is
to use an analog circuit instead of a digital circuit. This paper investigates
a continuous-time gradient flow-based approach for decoding LDPC codes, which
employs a potential energy function similar to the objective function used in
the gradient descent bit flipping (GDBF) algorithm. We experimentally
demonstrate that the decoding performance of the gradient flow decoding is
comparable to that of the multi-bit mode GDBF algorithm. Since an analog
circuit of the gradient flow decoding requires only analog arithmetic
operations and an integrator, future advancements in programmable analog
integrated circuits may make practical implementation feasible.Comment: 6 page
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