An Efficient Method to Improve the Audio Quality Using AAC Low Complexity Decoder

This paper presents a new approach to design a Digital Audio Broadcast (DAB) audio decoder is introduced to improve the superiority of audio. Countries all over the world use DAB broadcasting systems more prominently, in Europe. DAB+ is the upgraded version of digital audio broadcasting. DAB and DAB+ coexist in many countries, so receivers are essential to be compatible with both standards. DAB+ is approximately twice as efficient as DAB due to the adoption of the AAC+ audio codec, and DAB+ can provide high quality audio with bit rates as low as 64 kbit/s. Integrating an MPEG-1 Layer II (MP2) decoder and Advanced Audio Coding Low Complexity (AAC LC) decoder provides a fundamental audio decoding for DAB and DAB+. The generated audio frames data from the DAB channel decoders are stored in RAM. The bit stream demultiplexer parses the quantized spectrum data in the audio. The inverse quantization performs the inverse quantization computation and synthesis filter generates the time domain Pulse Code Modulation (PCM) samples, all the above operation results writes them back to the audio RAM. The existing system of this project uses HE AAC V2 decoder, that system consists has SBR and PS technologies. This two technologies are used to improve the sound quality in low bit rate program. The proposed scheme is uses AAC LC and MP2 decoder it improve the sound quality in high bit rate. The simulation of this project is carried out by using MATLAB R2011a and Xilinx ISE 9.2i. DOI: 10.17762/ijritcc2321-8169.15039

Multimedia broadcast and internet satellite system design and user trial results

The EU funded project, System for Advanced Multimedia Broadcast and IT Services (SAMBITS), has created an enhanced and synchronised, multimedia terminal for merging satellite broadcast and internet telecommunication services in a way that efficiently combines the large bandwidth of the broadcast channel and the interactivity of the internet. This paper proposes a novel broadcast and internet service concept, illustrates this concept with two service scenarios and develops a system architecture to demonstrate the range of key benefits provided by these new technologies. It then describes the interactive multimedia terminal that was used for consuming this new service concept. Finally, the results of the user trials on the terminal are presented and discussed

DRM analysis using a simulator of multiprocessor embedded system

Mestrado em Engenharia Electrónica e TelecomunicaçõesOs sistemas multiprocessador são uma tecnologia emergente. O projecto Hijdra, que está a ser desenvolvido na “NXP semiconductors Research” é um sistema multiprocessador de tempo real que corre aplicações com constrangimentos do tipo “hard” e “soft”. Nestes sistemas, os processadores comunicam através de uma rede de silício. As aplicações que correm no sistema multiprocessador consistem em múltiplas tarefas que correm em processadores embutidos. Achar soluções para o mapeamento das tarefas é o maior problema destes sistemas. Uma aplicação para este sistema que tem vindo a ser estudada é o “Car Radio”. Esta dissertação diz respeito a uma aplicação de rádio digital (DRM) na arquitectura Hijdra. Neste contexto, uma aplicação de um receptor de DRM foi estudada. Um modelo de análise de “Data Flow” foi extraído a partir da aplicação, foi estudada a latência introduzida na rede de silício pela introdução de um novo processador (acelerador de Viterbi) e foi estudada a possibilidade do mapeamento das várias tarefas da aplicação em diferentes processadores a correr em paralelo. Muitas estratégias ainda ficaram por definir a fim de optimizar o desempenho da aplicação do receptor de DRM de modo a esta poder trabalhar de uma forma mais eficaz. ABSTRACT: Multiprocessor systems are an emerging technology. The Hijdra project being developed at NXP semiconductors Research is a multiprocessor system running with both hard and soft real time streaming media jobs. These jobs consist of multiple tasks running on embedded multiprocessors. Finding good solutions for job mapping is the main problem of these systems. One application which has being studied for Hijdra is the “Car Radio”. This thesis concerns the study of a digital radio receptor application (DRM) in Hijdra architecture. In this context, a data flow model of analysis was extracted from the application, the latency introduced by the addition of a new tile (Viterbi accelerator) and eventual speed gains were studied and the possibility of mapping the different tasks of the application in different processors was foreseen. Many strategies were yet to be defined in order to optimize the application performance so it can work more effectively in the multiprocessor system

Exploring Processor and Memory Architectures for Multimedia

Multimedia has become one of the cornerstones of our 21st century society and, when combined with mobility, has enabled a tremendous evolution of our society. However, joining these two concepts introduces many technical challenges. These range from having sufficient performance for handling multimedia content to having the battery stamina for acceptable mobile usage. When taking a projection of where we are heading, we see these issues becoming ever more challenging by increased mobility as well as advancements in multimedia content, such as introduction of stereoscopic 3D and augmented reality. The increased performance needs for handling multimedia come not only from an ongoing step-up in resolution going from QVGA (320x240) to Full HD (1920x1080) a 27x increase in less than half a decade. On top of this, there is also codec evolution (MPEG-2 to H.264 AVC) that adds to the computational load increase. To meet these performance challenges there has been processing and memory architecture advances (SIMD, out-of-order superscalarity, multicore processing and heterogeneous multilevel memories) in the mobile domain, in conjunction with ever increasing operating frequencies (200MHz to 2GHz) and on-chip memory sizes (128KB to 2-3MB). At the same time there is an increase in requirements for mobility, placing higher demands on battery-powered systems despite the steady increase in battery capacity (500 to 2000mAh). This leaves negative net result in-terms of battery capacity versus performance advances. In order to make optimal use of these architectural advances and to meet the power limitations in mobile systems, there is a need for taking an overall approach on how to best utilize these systems. The right trade-off between performance and power is crucial. On top of these constraints, the flexibility aspects of the system need to be addressed. All this makes it very important to reach the right architectural balance in the system. The first goal for this thesis is to examine multimedia applications and propose a flexible solution that can meet the architectural requirements in a mobile system. Secondly, propose an automated methodology of optimally mapping multimedia data and instructions to a heterogeneous multilevel memory subsystem. The proposed methodology uses constraint programming for solving a multidimensional optimization problem. Results from this work indicate that using today’s most advanced mobile processor technology together with a multi-level heterogeneous on-chip memory subsystem can meet the performance requirements for handling multimedia. By utilizing the automated optimal memory mapping method presented in this thesis lower total power consumption can be achieved, whilst performance for multimedia applications is improved, by employing enhanced memory management. This is achieved through reduced external accesses and better reuse of memory objects. This automatic method shows high accuracy, up to 90%, for predicting multimedia memory accesses for a given architecture

API multiplataforma para aplicações multimídia embarcadas

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Ciência da Computação, Florianópolis, 2010Diferentes plataformas são utilizadas para o desenvolvimento de aplicações multimídia embarcadas. É comum que compiladores estejam disponíveis para estas plataformas porém, o código gerado a partir de linguagens de alto nível não é capaz de explorar todo o potencial do hardware da plataforma alvo. Para otimizar partes críticas da aplicação, geralmente são implementadas rotinas em linguagem de máquina (Assembly). Entretanto, o uso de linguagem Assembly na aplicação dificulta sua portabilidade para outras plataformas pois seu código necessita ser reescrito. A migração de uma aplicação para uma nova plataforma, com arquitetura e características de hardware diferentes, requer a reescrita do código da aplicação para a Interface para Programação de Aplicação (API) da arquitetura fornecida pelo fabricante. Este processo requer tempo, atrasando a criação de novos produtos, aumentando assim os custos de desenvolvimento e possivelmente resulta em aplicações ineficientes, que não exploram toda a potencialidade do hardware utilizado. Este trabalho apresenta a Embedded Multimedia Cross-Platform API (EMCA) que tem como objetivo fornecer ao desenvolvedor de aplicações multimídia uma interface independente de hardware para algoritmos de processamento de sinais digitais, facilitando a migração da aplicação para diferentes plataformas. Através do uso de mediadores de hardware a EMCA permite a implementação de algoritmos DSP independentes de plataforma. São expostos os mediadores de hardware de MAC e Barrel Shifter e a interface de Transformada Rápida de Fourier (FFT) da EMCA. Foi avaliada a utilização da EMCA em um decodificador de áudio Codificação de Áudio Avançada (AAC), mostrando que a sua especialização para arquiteturas embarcadas permite a otimização da aplicação sem comprometer sua portabilidade para outras plataformas

Reconfigurable media coding: a new specification model for multimedia coders

Multimedia coding technology, after about 20 years of active research, has delivered a rich variety of different and complex coding algorithms. Selecting an appropriate subset of these algorithms would, in principle, enable a designer to produce the codec supporting any desired functionality as well as any desired trade-off between compression performance and implementation complexity. Currently, interoperability demands that this selection process be hard-wired into the normative descriptions of the codec, or at a lower level, into a predefined number of choices, known as profiles, codified within each standard specification. This paper presents an alternative paradigm for codec deployment that is currently under development by MPEG, known as Reconfigurable Media Coding (RMC). Using the RMC framework, arbitrary combinations of fundamental algorithms may be assembled, without predefined standardization, because everything necessary for specifying the decoding process is delivered alongside the content itself. This side-information consists of a description of the bitstream syntax, as well as a description of the decoder configuration. Decoder configuration information is provided as a description of the interconnections between algorithmic blocks. The approach has been validated by development of an RMC format that matches MPEG-4 Video, and then extending the format by adding new chroma-subsampling patterns

Efficiency in audio processing : filter banks and transcoding

Audio transcoding is the conversion of digital audio from one compressed form A to another compressed form B, where A and B have different compression properties, such as a different bit-rate, sampling frequency or compression method. This is typically achieved by decoding A to an intermediate uncompressed form, and then encoding it to B. A significant portion of the involved computational effort pertains to operating the synthesis filter bank, which is an important processing block in the decoding stage, and the analysis filter bank, which is an important processing block in the encoding stage. This thesis presents methods for efficient implementations of filter banks and audio transcoders, and is separated into two main parts. In the first part, a new class of Frequency Response Masking (FRM) filter banks is introduced. These filter banks are usually characterized by comprising a tree-structured cascade of subfilters, which have small individual filter lengths. Methods of complexity reduction are proposed for the scenarios when the filter banks are operated in single-rate mode, and when they are operated in multirate mode; and for the scenarios when the input signal is real-valued, and when it is complex-valued. An efficient variable bandwidth FRM filter bank is designed by using signed-powers-of-two reduction of its subfilter coefficients. Our design has a complexity an order lower than that of an octave filter bank with the same specifications. In the second part, the audio transcoding process is analyzed. Audio transcoding is modeled as a cascaded quantization process, and the cascaded quantization of an input signal is analyzed under different conditions, for the MPEG 1 Layer 2 and MP3 compression methods. One condition is the input-to-output delay of the transcoder, which is known to have an impact on the audio quality of the transcoded material. Methods to reduce the error in a cascaded quantization process are also proposed. An ultra-fast MP3 transcoder that requires only integer operations is proposed and implemented in software. Our implementation shows an improvement by a factor of 5 to 16 over other best known transcoders in terms of execution speed

Coprojeto de um decodificador de áudio AAC-LC em FPGA

Dissertação (mestrado)—Universidade de Brasília, Instituto de Ciências Exatas, Departamento de Ciência da Computação, 2013.A Codificação de áudio está presente hoje nos mais diversos aparelhos eletrônicos desde o rádio, a televisão, o computador, os tocadores de música portáteis e nos celulares. Em 2007, o governo do Brasil definiu o padrão do Sistema Brasileiro de TV Digital (SBTVD) que adotou o AAC Advanced Audio Coding para codificação de áudio. Neste trabalho, utilizamos a abordagem de coprojeto combinando software e hardware para implementar uma solução de alto desempenho e baixo consumo de energia em um FPGA, capaz de decodificar até 6 canais de áudio em tempo real. Apresentamos os detalhes da solução bem como os testes de desempenho e qualidade. Por fim, apresentamos os resultados de utilização de hardware e performance juntamente com uma comparação com as demais soluções encontradas na literatura. _______________________________________________________________________________________ ABSTRACTAudio Coding is present today in many electronic devices. It can be found in radio, tv, computers, portable audio players and mobile phones. In 2007 the Brazilian Government defined the brazilian Digital TV System standard (SBTVD) and adopted the AAC - Advanced Audio Coding as the audio codec. In this work we use the co-design of hardware and software approach to implement a high performance and low energy solution on an FPGA, able to decode up to 6 channels of audio in real-time. The solution architecture and details are presented along with performance and quality tests. Finally, hardware usage and performance results are presented and compared to other solutions found in literature

A Wireless Brain-Machine Interface for Real-Time Speech Synthesis

Background: Brain-machine interfaces (BMIs) involving electrodes implanted into the human cerebral cortex have recently been developed in an attempt to restore function to profoundly paralyzed individuals. Current BMIs for restoring communication can provide important capabilities via a typing process, but unfortunately they are only capable of slow communication rates. In the current study we use a novel approach to speech restoration in which we decode continuous auditory parameters for a real-time speech synthesizer from neuronal activity in motor cortex during attempted speech. Methodology/Principal Findings: Neural signals recorded by a Neurotrophic Electrode implanted in a speech-related region of the left precentral gyrus of a human volunteer suffering from locked-in syndrome, characterized by near-total paralysis with spared cognition, were transmitted wirelessly across the scalp and used to drive a speech synthesizer. A Kalman filter-based decoder translated the neural signals generated during attempted speech into continuous parameters for controlling a synthesizer that provided immediate (within 50 ms) auditory feedback of the decoded sound. Accuracy of the volunteer's vowel productions with the synthesizer improved quickly with practice, with a 25% improvement in average hit rate (from 45% to 70%) and 46% decrease in average endpoint error from the first to the last block of a three-vowel task. Conclusions/Significance: Our results support the feasibility of neural prostheses that may have the potential to provide near-conversational synthetic speech output for individuals with severely impaired speech motor control. They also provide an initial glimpse into the functional properties of neurons in speech motor cortical areas.National Institute on Deafness and Other Communication Disorders (U.S.) (Grant R44-DC007050)National Institute on Deafness and Other Communication Disorders (U.S.) (Grant R01-DC007683)National Institute on Deafness and Other Communication Disorders (U.S.) (Grant R01-DC002852)Center of Excellence for Learning in Education, Science, and Technology (SBE-0354378