463 research outputs found

    Detection of Malicious Circuitry using Transition Probability Based Node Reduction Technique

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    In recent years, serious concerns have been raised against the tampering of integrated circuits due to outsourcing of circuits for fabrication. It has led to the addition of malicious circuitry known as Hardware Trojan. In this paper, a transition probability based node reduction technique for faster and efficient Hardware Trojan (HT) detection has been attempted. In the proposed method, the fact that the least controllable and observable nodes or the nodes with least transition probability are more vulnerable as Trojan sites is taken into consideration. The nodes that have lesser activity than the threshold are the candidate nodes. At each candidate node, segmentation is done for further leakage power analysis to detect the presence of Trojans. Experimental results observed on ISCAS’85 and ISCAS’89 benchmark circuits illustrate that the proposed work can achieve remarkable node reduction upto 78.81% and time reduction upto 58.7%. It was also observed that the circuit activity can be increased by varying the input probability. Hence, for further reduction in the Trojan activation time, the weighted input probability was obtained

    A Unified Framework for Multimodal Submodular Integrated Circuits Trojan Detection

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    Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation

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    The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation
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