On the minimum number of states for switchable matching networks

The impedance of an antenna changes heavily with changing EM environments, while RF power amplifiers (PAs) are optimized for driving a well-defined load impedance. As a solution, switchable matching networks are used in automatic antenna tuners to match the antenna impedance to (about) the desired PA load impedance. This paper presents a theoretical treaty of the minimum number of required states for switchable matching networks to achieve sufficient matching from a certain load VSWR to a sufficiently low input VSWR. First for an arbitrary passive lossless switchable matching network, the mathematical minimum required number of states as a function of the required input VSWR and of the required load VSWR is derived. Several variants are analyzed and benchmarked: single-stage one-ring configuration, single-stage two-ring configuration, two-stage one-ring configuration and three-stage one-ring configuration showing that single-ring configurations are optimum. An extension towards the required number of states for lossy matching networks is also provided

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

Energy-efficient hardware design based on high-level synthesis

This dissertation describes research activities broadly concerning the area of High-level synthesis (HLS), but more specifically, regarding the HLS-based design of energy-efficient hardware (HW) accelerators. HW accelerators, mostly implemented on FPGAs, are integral to the heterogeneous architectures employed in modern high performance computing (HPC) systems due to their ability to speed up the execution while dramatically reducing the energy consumption of computationally challenging portions of complex applications. Hence, the first activity was regarding an HLS-based approach to directly execute an OpenCL code on an FPGA instead of its traditional GPU-based counterpart. Modern FPGAs offer considerable computational capabilities while consuming significantly smaller power as compared to high-end GPUs. Several different implementations of the K-Nearest Neighbor algorithm were considered on both FPGA- and GPU-based platforms and their performance was compared. FPGAs were generally more energy-efficient than the GPUs in all the test cases. Eventually, we were also able to get a faster (in terms of execution time) FPGA implementation by using an FPGA-specific OpenCL coding style and utilizing suitable HLS directives. The second activity was targeted towards the development of a methodology complementing HLS to automatically derive power optimization directives (also known as "power intent") from a system-level design description and use it to drive the design steps after HLS, by producing a directive file written using the common power format (CPF) to achieve power shut-off (PSO) in case of an ASIC design. The proposed LP-HLS methodology reduces the design effort by enabling designers to infer low power information from the system-level description of a design rather than at the RTL. This methodology required a SystemC description of a generic power management module to describe the design context of a HW module also modeled in SystemC, along with the development of a tool to automatically produce the CPF file to accomplish PSO. Several test cases were considered to validate the proposed methodology and the results demonstrated its ability to correctly extract the low power information and apply it to achieve power optimization in the backend flow

Generic Adaptation Support for Wireless Sensor Networks

Wireless Sensor Networks are used in various and expanding application scenarios and are also considered to be important elements of the Internet of Things. They monitor and deliver data, which is not only used for research but to an increasing degree also in business environments. With the increasing complexity of these scenarios and the increasing dependency on the availability of the sensor network data, the requirements to a Wireless Sensor Network increase at the same pace. Since Wireless Sensor Networks are typically implemented using resource-constrained platforms, sensor network algorithms are typically optimised for specific operating conditions such as static or mobile networks, high or low traffic etc. However, due to scenario complexity and dynamic real-world conditions a static configuration of a Wireless Sensor Network software cannot always meet the requirements. Moreover, these requirements of the sensor network's user can change over time, for example concerning accuracy. Therefore, the sensor network software has to adapt itself to cope with dynamic system conditions and user requirements. This thesis presents the TinyAdapt and TinySwitch frameworks to solve the aforementioned problems. TinyAdapt, our generic adaptation framework for Wireless Sensor Networks, allows for the autonomous adaptation of arbitrary sensor network algorithms based on explicit and intuitively defined user preferences and on automatically monitored network conditions. Due to a two-phase approach, run-time adaptation is executed completely and efficiently on standard sensor node hardware and does not need support from, e.g., the base station. The creation of adaptive applications is guided by a complete workflow, which is presented as well. When changing parameters of an algorithm is not enough to achieve the desired adaptation results, the algorithm has to be exchanged completely. However, several limitations of TinyOS and the sensor node hardware limit the use of simple code exchange by node reprogramming for efficient adaptation. TinySwitch, our generic switching framework, allows to switch between alternative algorithms that are already installed in parallel. TinySwitch analyses these algorithms, determines their dependencies and creates all code to enable one of the algorithms while isolating all others. Due to its minimal overhead, TinySwitch is perfectly suited for run-time adaptation in TinyAdapt

Dynamic Optical Networks for Data Centres and Media Production

This thesis explores all-optical networks for data centres, with a particular focus on network designs for live media production. A design for an all-optical data centre network is presented, with experimental verification of the feasibility of the network data plane. The design uses fast tunable (< 200 ns) lasers and coherent receivers across a passive optical star coupler core, forming a network capable of reaching over 1000 nodes. Experimental transmission of 25 Gb/s data across the network core, with combined wavelength switching and time division multiplexing (WS-TDM), is demonstrated. Enhancements to laser tuning time via current pre-emphasis are discussed, including experimental demonstration of fast wavelength switching (< 35 ns) of a single laser between all combinations of 96 wavelengths spaced at 50 GHz over a range wider than the optical C-band. Methods of increasing the overall network throughput by using a higher complexity modulation format are also described, along with designs for line codes to enable pulse amplitude modulation across the WS-TDM network core. The construction of an optical star coupler network core is investigated, by evaluating methods of constructing large star couplers from smaller optical coupler components. By using optical circuit switches to rearrange star coupler connectivity, the network can be partitioned, creating independent reserves of bandwidth and resulting in increased overall network throughput. Several topologies for constructing a star from optical couplers are compared, and algorithms for optimum construction methods are presented. All of the designs target strict criteria for the flexible and dynamic creation of multicast groups, which will enable future live media production workflows in data centres. The data throughput performance of the network designs is simulated under synthetic and practical media production traffic scenarios, showing improved throughput when reconfigurable star couplers are used compared to a single large star. An energy consumption evaluation shows reduced network power consumption compared to incumbent and other proposed data centre network technologies

How to wire a 1000-qubit trapped ion quantum computer

One of the most formidable challenges of scaling up quantum computers is that of control signal delivery. Today's small-scale quantum computers typically connect each qubit to one or more separate external signal sources. This approach is not scalable due to the I/O limitations of the qubit chip, necessitating the integration of control electronics. However, it is no small feat to shrink control electronics into a small package that is compatible with qubit chip fabrication and operation constraints without sacrificing performance. This so-called "wiring challenge" is likely to impact the development of more powerful quantum computers even in the near term. In this paper, we address the wiring challenge of trapped-ion quantum computers. We describe a control architecture called WISE (Wiring using Integrated Switching Electronics), which significantly reduces the I/O requirements of ion trap quantum computing chips without compromising performance. Our method relies on judiciously integrating simple switching electronics into the ion trap chip - in a way that is compatible with its fabrication and operation constraints - while complex electronics remain external. To demonstrate its power, we describe how the WISE architecture can be used to operate a fully connected 1000-qubit trapped ion quantum computer using ~ 200 signal sources at a speed of ~ 40 - 2600 quantum gate layers per second