3,337 research outputs found

    Hardware Discrete Channel Emulator

    No full text
    International audienceIn this paper, the emulation environment named Hardware Discrete Channel Emulator (HDCE) has been developed as a coherent framework to emulate on a hardware device (FPGA as the implementation platform in the verification) and simulate on a computer the effect of an Additive White Gaussian Noise (AWGN) in a base band channel. The HDCE is able to generate more than 180 M samples per second for a very low hardware cost, which has been achieved in an efficient architecture. Using the HDCE, the performance evaluation of a coding scheme for a BER of 10−9 requires only one minute of emulation time

    Network emulation focusing on QoS-Oriented satellite communication

    Get PDF
    This chapter proposes network emulation basics and a complete case study of QoS-oriented Satellite Communication

    When should I use network emulation ?

    Get PDF
    The design and development of a complex system requires an adequate methodology and efficient instrumental support in order to early detect and correct anomalies in the functional and non-functional properties of the tested protocols. Among the various tools used to provide experimental support for such developments, network emulation relies on real-time production of impairments on real traffic according to a communication model, either realistically or not. This paper aims at simply presenting to newcomers in network emulation (students, engineers, ...) basic principles and practices illustrated with a few commonly used tools. The motivation behind is to fill a gap in terms of introductory and pragmatic papers in this domain. The study particularly considers centralized approaches, allowing cheap and easy implementation in the context of research labs or industrial developments. In addition, an architectural model for emulation systems is proposed, defining three complementary levels, namely hardware, impairment and model levels. With the help of this architectural framework, various existing tools are situated and described. Various approaches for modeling the emulation actions are studied, such as impairment-based scenarios and virtual architectures, real-time discrete simulation and trace-based systems. Those modeling approaches are described and compared in terms of services and we study their ability to respond to various designer needs to assess when emulation is needed

    When Should I Use Network Emulation?

    Get PDF
    The design and development of a complex system requires an adequate methodology and efficient instrumental support in order to early detect and correct anomalies in the functional and non-functional properties of the tested protocols. Among the various tools used to provide experimental support for such developments, network emulation relies on real-time production of impairments on real traffic according to a communication model, either realistically or not. This paper aims at simply presenting to newcomers in network emulation (students, engineers, ...) basic principles and practices illustrated with a few commonly used tools. The motivation behind is to fill a gap in terms of introductory and pragmatic papers in this domain. The study particularly considers centralized approaches, allowing cheap and easy implementation in the context of research labs or industrial developments. In addition, an architectural model for emulation systems is proposed, defining three complementary levels, namely hardware, impairment and model levels. With the help of this architectural framework, various existing tools are situated and described. Various approaches for modeling the emulation actions are studied, such as impairment-based scenarios and virtual architectures, real-time discrete simulation and trace-based systems. Those modeling approaches are described and compared in terms of services and we study their ability to respond to various designer needs to assess when emulation is needed

    IP-Level Satellite Link Emulation with KauNet

    Get PDF
    Distributed applications and transport protocols communicating over a satellite link may react very strongly to conditions specific to that kind of link. Providing a evaluation framework to allow tests of real implementations of such software in that context is quite a challenging task. In this paper we demonstrate how the use of the general-purpose KauNet IP-level emulator combined with satellite-specific packet loss patterns can help by reproducing losses and delays experienced on a satellite link with a simple Ethernet LAN setup. Such a platform is an essential tool for developers performing continuous testing as they provide new features for e.g. video codecs or transport-level software like DCCP and its congestion control components

    Hardware emulation of wireless communication fading channels

    Get PDF
    This dissertation investigates several main challenges to implementing hardware-based wireless fading channel emulators with emphasis on incorporating accurate correlation properties. Multiple-input multiple-output (MIMO) fading channels are usually triply-selective with three types of correlation: temporal correlation, inter-tap correlation, and spatial correlation. The proposed emulators implement the triply-selective fading Channel Impulse Response (CIR) by incorporating the three types of correlation into multiple uncorrelated frequency-flat Rayleigh fading waveforms while meeting real-time requirements for high data-rate, large-sized MIMO, and/or long CIR channels. Specifically, mixed parallel-serial computational structures are implemented for Kronecker products of the correlation matrices, which makes the best tradeoff between computational speed and hardware usage. Five practical fading channel examples are implemented for RF or underwater acoustic MIMO applications. The performance of the hardware emulators are verified with an Altera Field-Programmable Gate Array (FPGA) platform and the results match the software simulators in terms of statistical and correlation properties. The dissertation also contributes to the development of a 2-by-2 MIMO transceiver testbench that is used to measure real-world fading channels. Intensive channel measurements are performed for indoor fixed mobile-to-mobile channels and the estimated CIRs demonstrate the triply-selective correlation properties --Abstract, page iv

    On Simplification of Ray Tracing Channels in Radio Channel Emulators for Device Testing

    Get PDF

    MGSim - Simulation tools for multi-core processor architectures

    Get PDF
    MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a many-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.Comment: 33 pages, 22 figures, 4 listings, 2 table

    CABE : a cloud-based acoustic beamforming emulator for FPGA-based sound source localization

    Get PDF
    Microphone arrays are gaining in popularity thanks to the availability of low-cost microphones. Applications including sonar, binaural hearing aid devices, acoustic indoor localization techniques and speech recognition are proposed by several research groups and companies. In most of the available implementations, the microphones utilized are assumed to offer an ideal response in a given frequency domain. Several toolboxes and software can be used to obtain a theoretical response of a microphone array with a given beamforming algorithm. However, a tool facilitating the design of a microphone array taking into account the non-ideal characteristics could not be found. Moreover, generating packages facilitating the implementation on Field Programmable Gate Arrays has, to our knowledge, not been carried out yet. Visualizing the responses in 2D and 3D also poses an engineering challenge. To alleviate these shortcomings, a scalable Cloud-based Acoustic Beamforming Emulator (CABE) is proposed. The non-ideal characteristics of microphones are considered during the computations and results are validated with acoustic data captured from microphones. It is also possible to generate hardware description language packages containing delay tables facilitating the implementation of Delay-and-Sum beamformers in embedded hardware. Truncation error analysis can also be carried out for fixed-point signal processing. The effects of disabling a given group of microphones within the microphone array can also be calculated. Results and packages can be visualized with a dedicated client application. Users can create and configure several parameters of an emulation, including sound source placement, the shape of the microphone array and the required signal processing flow. Depending on the user configuration, 2D and 3D graphs showing the beamforming results, waterfall diagrams and performance metrics can be generated by the client application. The emulations are also validated with captured data from existing microphone arrays.</jats:p
    corecore