Hard-input-hard-output capacity analysis of UWB BPSK systems with timing errors

The hard-input-hard-output capacity of a binary phase-shift keying (BPSK) ultrawideband system is analyzed for both additive white Gaussian noise and multipath fading channels with timing errors. Unlike previous works that calculate the capacity with perfect synchronization and/or multiple-access interference only, our analysis considers timing errors with different distributions, as well as the interpath (IPI), interchip (ICI), and intersymbol (ISI) interferences, as in practical systems. The sensitivity of the channel capacity to the timing error is examined. The effects of pulse shape, the multiple-access technique, the number of users, and the number of chips are studied. It is found that time hopping is less sensitive to the pulse shape and that the timing error has higher capacity than direct sequence due to its low duty of cycle. Using these results, one can choose appropriate system parameters for different applications

UWB communication systems acquisition at symbol rate sampling for IEEE standard channel models

For ultra-wideband (UWB) communications, acquisition is challenging. The reason is from the ultra short pulse shape and ultra dense multipath interference. Ultra short pulse indicates the acquisition region is very narrow. Sampling is another challenge for UWB design due to the need for ultra high speed analog-to digital converter.A sub-optimum and under-sampling scheme using pilot codes as transmitted reference is proposed here for acquisition. The sampling rate for the receiver is at the symbol rate. A new architecture, the reference aided matched filter is studied in this project. The reference aided matched filter method avoids using complex rake receiver to estimate channel parameters and high sampling rate for interpolation. A limited number of matched filters are used as a filter bank to search for the strongest path. Timing offset for acquisition is then estimated and passed to an advanced verification algorithm. For optimum performance of acquisition, the adaptive post detection integration is proposed to solve the problem from dense inter-symbol interference during the acquisition. A low-complex early-late gate tracking loop is one element of the adaptive post detection integration. This tracking scheme assists in improving acquisition accuracy. The proposed scheme is evaluated using Matlab Simulink simulations in term of mean acquisition time, system performance and false alarm. Simulation results show proposed algorithm is very effective in ultra dense multipath channels. This research proves reference aided acquisition with tracking loop is promising in UWB application

Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe

A General Framework for Analyzing, Characterizing, and Implementing Spectrally Modulated, Spectrally Encoded Signals

Fourth generation (4G) communications will support many capabilities while providing universal, high speed access. One potential enabler for these capabilities is software defined radio (SDR). When controlled by cognitive radio (CR) principles, the required waveform diversity is achieved via a synergistic union called CR-based SDR. Research is rapidly progressing in SDR hardware and software venues, but current CR-based SDR research lacks the theoretical foundation and analytic framework to permit efficient implementation. This limitation is addressed here by introducing a general framework for analyzing, characterizing, and implementing spectrally modulated, spectrally encoded (SMSE) signals within CR-based SDR architectures. Given orthogonal frequency division multiplexing (OFDM) is a 4G candidate signal, OFDM-based signals are collectively classified as SMSE since modulation and encoding are spectrally applied. The proposed framework provides analytic commonality and unification of SMSE signals. Applicability is first shown for candidate 4G signals, and resultant analytic expressions agree with published results. Implementability is then demonstrated in multiple coexistence scenarios via modeling and simulation to reinforce practical utility