Split-enabled 350–630 Gb/s optical interconnect with direct detection NOMA-CAP and 7-core multi-core fiber

The ever-growing data traffic volume inside data centers caused by the popularization of cloud services and edge computing demands scalable and cost-efficient network infrastructures. With this premise, optical interconnects have recently gained more and more research attention as a key building block to ensure end-to-end energy efficient solutions, offering high throughput, low latency and reduced energy consumption compared to current networks based on active optical cables. An efficient way for performing such optical interconnects is to make use of multi-core fibers (MCFs), which enables the multiplexing of several spatial channels, each using a different core inside the same fiber cladding. Moreover, non-orthogonal multiple access combined with multi-band carrierless amplitude and phase modulation (NOMA-CAP) has been recently proposed as a potential candidate to increase the network capacity and an efficiency/flexibility resource management. In this paper, using direct detection we experimentally demonstrate the transmission of NOMA-CAP signals through a 2 km MCF with 7 spatial channels for high capacity optical interconnect applications. The results show negligible transmission penalty for different total aggregated traffics ranging from 350 Gb/s to 630 Gb/s.This work was supported in part by ALLIANCE (TEC2017-90034-C2-2-R) project co-funded by FEDER, the European Union’s Horizon 2020 research and innovation programme under grant agreement no780997 (plaCMOS), as well as MINECO FPI-BES-2015-074302Peer ReviewedPostprint (author's final draft

Equalizer State Caching for Fast Data Recovery in Optically-Switched Data Center Networks

Optical switching offers the potential to significantly scale the capacity of data center networks (DCN) with a simultaneous reduction in switching time and power consumption. Previous research has shown that end-to-end switching time, which is the sum of the switch configuration time and the clock and data recovery (CDR) locking time, should be kept within a few nanoseconds for high network throughput. This challenge of low switching time has motivated research into fast optical switches, ultra-fast clock and amplitude recovery techniques. Concurrently, the data rate between server-to-server and server-to-switch interconnect is increasing drastically from the current 100 Gb/s (4×25 Gb/s) to 400 Gb/s and beyond, motivating the use of high order formats such as 50-GBaud four-level pulse-amplitude modulation (PAM-4) for signalling. Since PAM-4 is more sensitive to noise and distortion, digital equalizers are generally needed to compensate for impairments such as transceiver frequency rolloff, dispersion and optical filtering, adding additional time for equalizer adaptation and power consumption that are undesired for fast optical switching systems. Here we propose and investigate an equalizer state caching technique that reduces equalizer adaptation time and computation power consumption for fast optical switching systems, underpinning optically-switched DCNs using high baud rate and impairment-sensitive formats. Through a proof-of-concept experiment, we study the performance of the proposed equalizer state caching scheme in a three-node optical switching system using 56 GBaud PAM-4. Our experimental results show that the proposed scheme can tolerate up to 0.8-nm (100-GHz) instantaneous wavelength change with an adaptation delay of only 0.36 ns. Practical considerations such as clock phase misalignment, temperature-induced wavelength drift, and equalizer precision are also studied

FPGA-Implemented Fractal Decoder with Forward Error Correction in Short-Reach Optical Interconnects

Forward error correction (FEC) codes combined with high-order modulator formats, i.e., coded modulation (CM), are essential in optical communication networks to achieve highly efficient and reliable communication. The task of providing additional error control in the design of CM systems with high-performance requirements remains urgent. As an additional control of CM systems, we propose to use indivisible error detection codes based on a positional number system. In this work, we evaluated the indivisible code using the average probability method (APM) for the binary symmetric channel (BSC), which has the simplicity, versatility and reliability of the estimate, which is close to reality. The APM allows for evaluation and compares indivisible codes according to parameters of correct transmission, and detectable and undetectable errors. Indivisible codes allow for the end-to-end (E2E) control of the transmission and processing of information in digital systems and design devices with a regular structure and high speed. This study researched a fractal decoder device for additional error control, implemented in field-programmable gate array (FPGA) software with FEC for short-reach optical interconnects with multilevel pulse amplitude (PAM-M) modulated with Gray code mapping. Indivisible codes with natural redundancy require far fewer hardware costs to develop and implement encoding and decoding devices with a sufficiently high error detection efficiency. We achieved a reduction in hardware costs for a fractal decoder by using the fractal property of the indivisible code from 10% to 30% for different n while receiving the reciprocal of the golden ratio

Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications

The rapid proliferation of the Internet has been driving communication networks closer and closer to their limits, while available bandwidth is disappearing due to an ever-increasing network load. Over the past decade, optical fiber communication technology has increased per fiber data rate from 10 Tb/s to exceeding 10 Pb/s. The major explosion came after the maturity of coherent detection and advanced digital signal processing (DSP). DSP has played a critical role in accommodating channel impairments mitigation, enabling advanced modulation formats for spectral efficiency transmission and realizing flexible bandwidth. This book aims to explore novel, advanced DSP techniques to enable multi-Tb/s/channel optical transmission to address pressing bandwidth and power-efficiency demands. It provides state-of-the-art advances and future perspectives of DSP as well

Low-Complexity Soft-Decision Detection for Combating DFE Burst Errors in IM/DD Links

The deployment of non-binary pulse amplitude modulation (PAM) and soft decision (SD)-forward error correction (FEC) in future intensity-modulation (IM)/direct-detection (DD) links is inevitable. However, high-speed IM/DD links suffer from inter-symbol interference (ISI) due to bandwidth-limited hardware. Traditional approaches to mitigate the effects of ISI are filters and trellis-based algorithms targeting symbol-wise maximum a posteriori (MAP) detection. The former approach includes decision-feedback equalizer (DFE), and the latter includes Max-Log-MAP (MLM) and soft-output Viterbi algorithm (SOVA). Although DFE is easy to implement, it introduces error propagation. Such burst errors distort the log-likelihood ratios (LLRs) required by SD-FEC, causing performance degradation. On the other hand, MLM and SOVA provide near-optimum performance, but their complexity is very high for high-order PAM. In this paper, we consider a one-tap partial response channel model, which is relevant for high-speed IM/DD links. We propose to combine DFE with either MLM or SOVA in a low-complexity architecture. The key idea is to allow MLM or SOVA to detect only 3 typical DFE symbol errors, and use the detected error information to generate LLRs in a modified demapper. The proposed structure enables a tradeoff between complexity and performance: (i) the complexity of MLM or SOVA is reduced and (ii) the decoding penalty due to error propagation is mitigated. Compared to SOVA detection, the proposed scheme can achieve a significant complexity reduction of up to 94% for PAM-8 transmission. Simulation and experimental results show that the resulting SNR loss is roughly 0.3 to 0.4 dB for PAM-4, and becomes marginal 0.18 dB for PAM-8.Comment: This manuscript has been submitted to JL

Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient Computing

With the explosion of the number of compute nodes, the bottleneck of future computing systems lies in the network architecture connecting the nodes. Addressing the bottleneck requires replacing current backplane-based network topologies. We propose to revolutionize computing electronics by realizing embedded optical waveguides for onboard networking and wireless chip-to-chip links at 200-GHz carrier frequency connecting neighboring boards in a rack. The control of novel rate-adaptive optical and mm-wave transceivers needs tight interlinking with the system software for runtime resource management