147 research outputs found

    Building real-time embedded applications on QduinoMC: a web-connected 3D printer case study

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    Single Board Computers (SBCs) are now emerging with multiple cores, ADCs, GPIOs, PWM channels, integrated graphics, and several serial bus interfaces. The low power consumption, small form factor and I/O interface capabilities of SBCs with sensors and actuators makes them ideal in embedded and real-time applications. However, most SBCs run non-realtime operating systems based on Linux and Windows, and do not provide a user-friendly API for application development. This paper presents QduinoMC, a multicore extension to the popular Arduino programming environment, which runs on the Quest real-time operating system. QduinoMC is an extension of our earlier single-core, real-time, multithreaded Qduino API. We show the utility of QduinoMC by applying it to a specific application: a web-connected 3D printer. This differs from existing 3D printers, which run relatively simple firmware and lack operating system support to spool multiple jobs, or interoperate with other devices (e.g., in a print farm). We show how QduinoMC empowers devices with the capabilities to run new services without impacting their timing guarantees. While it is possible to modify existing operating systems to provide suitable timing guarantees, the effort to do so is cumbersome and does not provide the ease of programming afforded by QduinoMC.http://www.cs.bu.edu/fac/richwest/papers/rtas_2017.pdfAccepted manuscrip

    Autonomous Machine์„ ์œ„ํ•œ ์‹ค์‹œ๊ฐ„ ์ŠคํŠธ๋ฆผ ์ฒ˜๋ฆฌ์™€ ์„ผ์„œ ํ“จ์ „์„ ์ง€์›ํ•˜๋Š” Splash ํ”„๋กœ๊ทธ๋ž˜๋ฐ ์–ธ์–ด์˜ ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ)--์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› :๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ปดํ“จํ„ฐ๊ณตํ•™๋ถ€,2020. 2. ํ™์„ฑ์ˆ˜.Autonomous machines have begun to be widely used in various application domains due to recent remarkable advances in machine intelligence. As these autonomous machines are equipped with diverse sensors, multicore processors and distributed computing nodes, the complexity of the underlying software platform is increasing at a rapid pace, overwhelming the developers with implementation details. This leads to a demand for a new programming framework that has an easy-to-use programming abstraction. In this thesis, we present a graphical programming framework named Splash that explicitly addresses the programming challenges that arise during the development of an autonomous machine. We set four design goals to solve the challenges. First, Splash should provide an easy-to-use, effective programming abstraction. Second, it must support real-time stream processing for deep-learning based machine learning intelligence. Third, it must provide programming support for real-time control system of autonomous machines such as sensor fusion and mode change. Finally, it should support performance optimization of software system running on a heterogeneous multicore distributed computing platform. Splash allows programmers to specify genuine, end-to-end timing constraints. Also, it provides a best-effort runtime system that tries to meet the annotated timing constraints and exception handling mechanisms to monitor the violation of such constraints. To implement these runtime mechanisms, Splash provides underlying timing semantics: (1) it provides an abstract global clock that is shared by machines in the distributed system and (2) it supports programmers to write birthmark on every stream data item. Splash offers a multithreaded process model to support concurrent programming. In the multithreaded process model, a programmer can write a multithreaded program using Splash threads we call sthreads. An sthread is a logical entity of independent execution. In addition, Splash provides a language construct named build unit that allows programmers to allocate sthreads to processes and threads of an underlying operating system. Splash provides three additional language semantics to support real-time stream processing and real-time control systems. First, it provides rate control semantics to solve uncontrolled jitter and an unbounded FIFO queue problem due to the variability in communication delay and execution time. Second, it supports fusion semantics to handle timing issues caused by asynchronous sensors in the system. Finally, it provides mode change semantics to meet varying requirements in the real-time control systems. In this paper, we describe each language semantics and runtime mechanism that realizes such semantics in detail. To show the utility of our framework, we have written a lane keeping assist system (LKAS) in Splash as an example. We evaluated rate control, sensor fusion, mode change and build unit-based allocation. First, using rate controller, the jitter was reduced from 30.61 milliseconds to 1.66 milliseconds. Also, average lateral deviation and heading angle is reduced from 0.180 meters to 0.016 meters and 0.043 rad to 0.008 rad, respectively. Second, we showed that the fusion operator works normally as intended, with a run-time overhead of only 7 microseconds on average. Third, the mode change mechanism operated correctly and incurred a run-time overhead of only 0.53 milliseconds. Finally, as we increased the number of build units from 1 to 8, the average end-to-end latency was increased from 75.79 microseconds to 2022.96 microseconds. These results show that the language semantics and runtime mechanisms proposed in this thesis are designed and implemented correctly, and Splash can be used to effectively develop applications for an autonomous machine.๋”ฅ ๋Ÿฌ๋‹ ๊ธฐ๋ฐ˜ machine intelligence์˜ ๋น„์•ฝ์ ์ธ ๋ฐœ์ „์œผ๋กœ ์ธํ•ด autonomous machine๋“ค์ด ๋‹ค์–‘ํ•œ ๋ถ„์•ผ์—์„œ ํ™œ์šฉ๋˜๊ณ  ์žˆ๋‹ค. ์ด๋Ÿฐ ๊ธฐ๊ธฐ๋“ค์€ ๋‹ค์–‘ํ•œ ์„ผ์„œ, ๋ฉ€ํ‹ฐ์ฝ”์–ด ํ”„๋กœ์„ธ์„œ, ๋ถ„์‚ฐ ์ปดํ“จํŒ… ๋…ธ๋“œ๋ฅผ ์žฅ์ฐฉํ•˜๊ณ  ์žˆ๊ธฐ ๋•Œ๋ฌธ์—, ์ด๋“ค์„ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•œ ๊ธฐ๋ฐ˜ ์†Œํ”„ํŠธ์›จ์–ด ํ”Œ๋žซํผ์˜ ๋ณต์žก๋„๋Š” ๋น ๋ฅธ ์†๋„๋กœ ์ฆ๊ฐ€ํ•˜๋Š” ์ถ”์„ธ์ด๋‹ค. ์ด์— ๋”ฐ๋ผ ๊ฐœ๋ฐœ์ž๋“ค์ด ๋ณต์žกํ•œ ์†Œํ”„ํŠธ์›จ์–ด ๊ตฌ์กฐ๋ฅผ ํšจ๊ณผ์ ์œผ๋กœ ๋‹ค๋ฃฐ ์ˆ˜ ์žˆ๋„๋ก ํ•ด์ฃผ๋Š” ํ”„๋กœ๊ทธ๋ž˜๋ฐ ํ”„๋ ˆ์ž„์›Œํฌ์˜ ํ•„์š”์„ฑ์ด ๋Œ€๋‘๋˜๊ณ  ์žˆ๋‹ค. ๋ณธ ํ•™์œ„๋…ผ๋ฌธ์€ autonomous machine์˜ ๊ฐœ๋ฐœ ๊ณผ์ •์—์„œ ๋ฐœ์ƒํ•˜๋Š” ๋ฌธ์ œ๋“ค์„ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•œ ๊ทธ๋ž˜ํ”ฝ ๊ธฐ๋ฐ˜ ํ”„๋กœ๊ทธ๋ž˜๋ฐ ํ”„๋ ˆ์ž„์›Œํฌ์ธ Splash๋ฅผ ์ œ์•ˆํ•œ๋‹ค. Splash๋ผ๋Š” ์ด๋ฆ„์€ stream processing language for autonomous machine์—์„œ ์•ž์˜ ์„ธ ๋‹จ์–ด์˜ ์ฒซ ๋ฌธ์ž๋“ค์„ ๋”ฐ์„œ ์ง€์–ด์กŒ๋‹ค. ์ด ์ด๋ฆ„์€ ๋ฌผ๊ณผ ๊ฐ™์ด ํ๋ฅด๋Š” ์ŠคํŠธ๋ฆผ ๋ฐ์ดํ„ฐ๋ฅผ ๋‹ค๋ฃจ๊ธฐ ์œ„ํ•œ ํ”„๋กœ๊ทธ๋ž˜๋ฐ ์–ธ์–ด์™€ ๋Ÿฐํƒ€์ž„ ์‹œ์Šคํ…œ์„ ๊ฐœ๋ฐœํ•˜๊ฒ ๋‹ค๋Š” ์˜๋„๋ฅผ ๊ฐ€์ง„๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ๋ณต์žกํ•œ ์†Œํ”„ํŠธ์›จ์–ด ๊ตฌ์กฐ๋ฅผ ํšจ๊ณผ์ ์œผ๋กœ ๋‹ค๋ฃจ๊ธฐ ์œ„ํ•ด ๋„ค ๊ฐ€์ง€ ๋””์ž์ธ ๋ชฉํ‘œ๋ฅผ ์„ค์ •ํ•œ๋‹ค. ์ฒซ์งธ, Splash๋Š” ๊ฐœ๋ฐœ์ž์—๊ฒŒ ์„ธ๋ถ€์ ์ธ ๊ตฌํ˜„ ์ด์Šˆ๋ฅผ ์ˆจ๊ธฐ๊ณ , ์‰ฝ๊ฒŒ ์‚ฌ์šฉํ•  ์ˆ˜ ์žˆ๋Š” ํ”„๋กœ๊ทธ๋ž˜๋ฐ ์ถ”์ƒํ™”๋ฅผ ์ œ๊ณตํ•˜์—ฌ์•ผ ํ•œ๋‹ค. ๋‘˜์งธ, Splash๋Š” machine intelligence๋ฅผ ์œ„ํ•œ ์‹ค์‹œ๊ฐ„ ์ŠคํŠธ๋ฆผ ์ฒ˜๋ฆฌ๋ฅผ ์ง€์›ํ•  ์ˆ˜ ์žˆ์–ด์•ผ ํ•œ๋‹ค. ์…‹์งธ, Splash๋Š” ์‹ค์‹œ๊ฐ„ ์ œ์–ด ์‹œ์Šคํ…œ์—์„œ ๋„๋ฆฌ ์‚ฌ์šฉ๋˜๋Š” ์„ผ์„œ ํ“จ์ „, ๋ชจ๋“œ ๋ณ€๊ฒฝ, ์˜ˆ์™ธ ์ฒ˜๋ฆฌ์™€ ๊ฐ™์€ ๊ธฐ๋Šฅ๋“ค์„ ์œ„ํ•œ ์ง€์›์„ ์ œ๊ณตํ•˜์—ฌ์•ผ ํ•œ๋‹ค. ๋„ท์งธ, Splash๋Š” ์ด๊ธฐ์ข… ๋ฉ€ํ‹ฐ์ฝ”์–ด ๋ถ„์‚ฐ ์ปดํ“จํŒ… ํ”Œ๋žซํผ์—์„œ ์ˆ˜ํ–‰๋˜๋Š” ์†Œํ”„ํŠธ์›จ์–ด ์‹œ์Šคํ…œ์˜ ์„ฑ๋Šฅ ์ตœ์ ํ™”๋ฅผ ์ง€์›ํ•˜์—ฌ์•ผ ํ•œ๋‹ค. Splash๋Š” ์‹ค์‹œ๊ฐ„ ์ŠคํŠธ๋ฆผ ์ฒ˜๋ฆฌ๋ฅผ ์œ„ํ•ด ๊ฐœ๋ฐœ์ž๊ฐ€ ํ”„๋กœ๊ทธ๋žจ ์ƒ์— ๋ณธ์งˆ์ ์ธ end-to-end timing constraints๋ฅผ ๋ช…์‹œํ•  ์ˆ˜ ์žˆ๋„๋ก ํ•œ๋‹ค. ๊ทธ๋ฆฌ๊ณ  ๊ฐœ๋ฐœ์ž๊ฐ€ ๋ช…์‹œํ•œ timing constraints๋ฅผ ์ธ์ง€ํ•˜๊ณ  ์ด๋ฅผ ์ตœ๋Œ€ํ•œ ์ง€์ผœ์ฃผ๋Š” best-effort ๋Ÿฐํƒ€์ž„ ์‹œ์Šคํ…œ๊ณผ timing constraints์˜ ์œ„๋ฐ˜์„ ๋ชจ๋‹ˆํ„ฐ๋งํ•˜๊ณ  ์ฒ˜๋ฆฌํ•ด์ฃผ๋Š” ์˜ˆ์™ธ ์ฒ˜๋ฆฌ ๋ฉ”์ปค๋‹ˆ์ฆ˜์„ ํ•จ๊ป˜ ์ œ๊ณตํ•œ๋‹ค. ์ด๋Ÿฐ ๋Ÿฐํƒ€์ž„ ๋ฉ”์ปค๋‹ˆ์ฆ˜๋“ค์„ ๊ตฌํ˜„ํ•˜๊ธฐ ์œ„ํ•ด Splash๋Š” ๋‘ ๊ฐ€์ง€ ๊ธฐ๋ณธ์ ์ธ timing semantics๋ฅผ ์ œ๊ณตํ•œ๋‹ค. ์ฒซ์งธ, ๋ถ„์‚ฐ ์‹œ์Šคํ…œ ์ƒ์—์„œ ๋ชจ๋“  ๋จธ์‹ ๋“ค์ด ๊ณต์œ ํ•  ์ˆ˜ ์žˆ๋Š” global time base๋ฅผ ์ œ๊ณตํ•œ๋‹ค. ๋‘˜์งธ, Splash ์ƒ์— ๋“ค์–ด์˜ค๋Š” ๋ชจ๋“  ์ŠคํŠธ๋ฆผ ๋ฐ์ดํ„ฐ ์•„์ดํ…œ์— ์ž์‹ ์˜ birthmark๋ฅผ ๊ธฐ๋กํ•˜๋„๋ก ํ•œ๋‹ค. Splash๋Š” ๋™์‹œ์„ฑ ํ”„๋กœ๊ทธ๋ž˜๋ฐ์„ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•œ ๋ฉ€ํ‹ฐ ์“ฐ๋ ˆ๋””๋“œ ์ฒ˜๋ฆฌ ๋ชจ๋ธ์„ ์ œ๊ณตํ•œ๋‹ค. Splash ํ”„๋กœ๊ทธ๋ž˜๋จธ๋Š” sthread๋ผ๋Š” ๋…ผ๋ฆฌ์ ์ธ ์ˆ˜ํ–‰ ๋‹จ์œ„๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ ํ”„๋กœ๊ทธ๋žจ์„ ๊ฐœ๋ฐœํ•  ์ˆ˜ ์žˆ๋‹ค. ๊ทธ๋ฆฌ๊ณ  Splash๋Š” sthread๋“ค์„ ์‹ค์ œ ์šด์˜์ฒด์ œ์˜ ์ˆ˜ํ–‰ ๋‹จ์œ„์ธ ํ”„๋กœ์„ธ์Šค์™€ ์“ฐ๋ ˆ๋“œ์—๊ฒŒ ํ• ๋‹นํ•˜๋Š” ๊ณผ์ •์„ ๋•๊ธฐ ์œ„ํ•œ ๋นŒ๋“œ ์œ ๋‹›์ด๋ผ๋Š” language construct๋ฅผ ์ œ๊ณตํ•œ๋‹ค. Splash๋Š” timing semantics์™€ ๋ฉ€ํ‹ฐ ์“ฐ๋ ˆ๋””๋“œ ์ฒ˜๋ฆฌ ๋ชจ๋ธ์„ ๊ธฐ๋ฐ˜์œผ๋กœ ์‹ค์‹œ๊ฐ„ ์ŠคํŠธ๋ฆผ ์ฒ˜๋ฆฌ์™€ ์‹ค์‹œ๊ฐ„ ์ œ์–ด ์‹œ์Šคํ…œ์„ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•œ ์„ธ ๊ฐ€์ง€ language semantics๋ฅผ ์ถ”๊ฐ€๋กœ ์ง€์›ํ•œ๋‹ค. ์ฒซ์งธ๋Š” ์ŠคํŠธ๋ฆผ ๋ฐ์ดํ„ฐ์˜ ํ†ต์‹ ์ด๋‚˜ ์ฒ˜๋ฆฌ ์ง€์—ฐ์œผ๋กœ ์ธํ•ด ๋ฐœ์ƒํ•˜๋Š” ์ง€ํ„ฐ๋‚˜ ๋ฐ”์šด๋“œ ๋˜์ง€ ์•Š๋Š” ํ ๋ฌธ์ œ๋ฅผ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•œ rate ์ œ์–ด semantics์ด๋‹ค. ๋‘˜์งธ๋Š” ์„ผ์„œ ํ“จ์ „ ๊ณผ์ •์—์„œ ์‹œ๊ฐ„์ ์œผ๋กœ ๋™๊ธฐํ™”๋˜์ง€ ์•Š์€ ์„ผ์„œ ์ž…๋ ฅ๋“ค๋กœ ์ธํ•œ ํƒ€์ด๋ฐ ์ด์Šˆ๋“ค์„ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•œ ํ“จ์ „ semantics์ด๋‹ค. ๋งˆ์ง€๋ง‰์€ ๊ฐ€๋ณ€์ ์ธ ์ œ์–ด ์‹œ์Šคํ…œ์˜ ์š”๊ตฌ์‚ฌํ•ญ์„ ์ถฉ์กฑ์‹œํ‚ค๊ธฐ ์œ„ํ•ด ์ˆ˜ํ–‰ ๋กœ์ง์˜ ๋ณ€๊ฒฝ์„ ์ง€์›ํ•˜๋Š” ๋ชจ๋“œ ๋ณ€๊ฒฝ semantics์ด๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ๊ฐ๊ฐ์˜ language semantics๋ฅผ ๊ตฌ์ฒด์ ์œผ๋กœ ์„ค๋ช…ํ•˜๊ณ , ์ด๋ฅผ ์‹คํ˜„ํ•˜๊ธฐ ์œ„ํ•œ ๋Ÿฐํƒ€์ž„ ๋ฉ”์ปค๋‹ˆ์ฆ˜์„ ์„ค๊ณ„ํ•˜๊ณ  ๊ตฌํ˜„ํ•œ๋‹ค. Splash์˜ ํšจ์šฉ์„ฑ์„ ๊ฒ€์ฆํ•˜๊ธฐ ์œ„ํ•ด์„œ, ๋ณธ ๋…ผ๋ฌธ์€ Splash๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ LKAS ์‘์šฉ์„ ๊ฐœ๋ฐœํ•˜๊ณ  ์ด๋ฅผ Splash ๋Ÿฐํƒ€์ž„ ์‹œ์Šคํ…œ ์ƒ์—์„œ ์ˆ˜ํ–‰์‹œํ‚ค๋ฉฐ ์‹คํ—˜์„ ์ง„ํ–‰ํ•˜์˜€๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” rate ์ œ์–ด ๋ฉ”์ปค๋‹ˆ์ฆ˜, ์„ผ์„œ ํ“จ์ „ ๋ฉ”์ปค๋‹ˆ์ฆ˜, ๋ชจ๋“œ ๋ณ€๊ฒฝ ๋ฉ”์ปค๋‹ˆ์ฆ˜, ๋นŒ๋“œ ์œ ๋‹› ๊ธฐ๋ฐ˜ allocation์„ ๊ฐ๊ฐ ์„ ์ •๋œ ์„ฑ๋Šฅ ์ง€ํ‘œ๋“ค์„ ์‚ฌ์šฉํ•˜์—ฌ ๊ฒ€์ฆํ•˜์˜€๋‹ค. ์ฒซ์งธ, Splash์˜ rate ์ œ์–ด๊ธฐ๋ฅผ ์‚ฌ์šฉํ•˜๋ฉด ์ง€ํ„ฐ๊ฐ€ 30.61ms์—์„œ 1.66ms๋กœ ๊ฐ์†Œ๋˜์—ˆ๊ณ , ์ด๋กœ ์ธํ•ด ์ฃผํ–‰ ์ฐจ๋Ÿ‰์˜ ์ธก๋ฉด ํŽธ์ฐจ์™€ ๋ฐฉํ–ฅ๊ฐ์ด ๊ฐ๊ฐ 0.180m์—์„œ 0.016m, 0.043rad์—์„œ 0.008rad์œผ๋กœ ๊ฐœ์„ ๋œ๋‹ค๋Š” ๊ฒƒ์„ ํ™•์ธํ•˜์˜€๋‹ค. ๋‘˜์งธ, ์„ผ์„œ ํ“จ์ „์„ ์œ„ํ•ด ์ œ์•ˆ๋œ ํ“จ์ „ ์—ฐ์‚ฐ์ž๊ฐ€ ์„ค๊ณ„๋œ ์˜๋„๋Œ€๋กœ ์ •์ƒ ๋™์ž‘ํ•˜๊ณ , ํ‰๊ท  7us์˜ ๋‚ฎ์€ ์˜ค๋ฒ„ํ—ค๋“œ๋งŒ์„ ์œ ๋ฐœํ•œ๋‹ค๋Š” ๊ฒƒ์„ ํ™•์ธํ•˜์˜€๋‹ค. ์…‹์งธ, ๋ชจ๋“œ ๋ณ€๊ฒฝ ๊ธฐ๋Šฅ์˜ ์ •์ƒ ๋™์ž‘์„ ๊ฒ€์ฆํ•˜์˜€๊ณ  ๊ทธ ๊ณผ์ •์—์„œ ๋ฐœ์ƒํ•˜๋Š” ์‹œ๊ฐ„์  ์˜ค๋ฒ„ํ—ค๋“œ๋Š” ํ‰๊ท  0.53ms์— ๋ถˆ๊ณผํ•˜์˜€๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ, synthetic workload์— ๋Œ€ํ•ด ์ปดํฌ๋„ŒํŠธ๋“ค์— ๋งคํ•‘๋œ ๋นŒ๋“œ ์œ ๋‹› ๊ฐœ์ˆ˜๋ฅผ 1๊ฐœ, 2๊ฐœ, 4๊ฐœ, 8๊ฐœ๋กœ ์ฆ๊ฐ€์‹œํ‚ด์— ๋”ฐ๋ผ ํ‰๊ท  end-to-end ์ง€์—ฐ ์‹œ๊ฐ„์€ 75.79us, 330.80us, 591.87us, 2022.96us๋กœ ์ฆ๊ฐ€ํ•˜๋Š” ๊ฒƒ์„ ํ™•์ธํ•˜์˜€๋‹ค. ์ด๋Ÿฌํ•œ ๊ฒฐ๊ณผ๋“ค์€ ๋ณธ ๋…ผ๋ฌธ์—์„œ ์ œ์•ˆํ•˜๋Š” language semantics์™€ ๋Ÿฐํƒ€์ž„ ๋ฉ”์ปค๋‹ˆ์ฆ˜๋“ค์ด ์˜๋„๋Œ€๋กœ ์„ค๊ณ„, ๊ตฌํ˜„๋˜์—ˆ๊ณ , ์ด๋ฅผ ํ†ตํ•ด autonomous machine์˜ ์‘์šฉ๋“ค์„ ํšจ๊ณผ์ ์œผ๋กœ ๊ฐœ๋ฐœํ•  ์ˆ˜ ์žˆ๋‹ค๋Š” ๊ฒƒ์„ ๋ณด์—ฌ์ค€๋‹ค.Chapter 1 Introduction p.1 1.1 Motivation p.2 1.2 Splash Overview p.5 1.3 Organization of This Dissertation p.9 Chapter 2 Related Work p.10 2.1 Kahn Process Network p.10 2.2 Firing Rule Applied to a Process p.13 2.3 Programming Framework for an Autonomous Machine p.14 2.4 Runtime Software for an Autonomous Machine p.16 2.5 Rate Control p.18 2.5.1 Traffic Shaping p.20 2.5.2 Traffic Policing p.22 2.6 Sensor Fusion p.23 2.6.1 Measurement Fusion p.24 2.6.2 Situation Fusion p.27 2.7 Mode Change p.30 2.7.1 Synchronous Mode Change p.32 2.7.2 Asynchronous Mode Change p.32 Chapter 3 Motivation and Contributions p.34 3.1 Problem Description p.34 3.2 Limitations of Kahn Process Network p.36 3.3 Contributions of this Dissertation p.38 Chapter 4 Underlying Timing Semantics of Splash p.41 4.1 End-to-End Timing Constraints p.41 4.2 Global Time Base and In-order Delivery p.42 4.3 Integrating Three Distinct Computing Models p.43 Chapter 5 Splash Language Constructs p.45 5.1 Processing Component p.46 5.2 Port p.49 5.3 Channel and Clink p.52 5.4 Fusion Operator p.54 5.5 Factory and Mode Change p.60 5.6 Build Unit p.65 5.7 Exception Handling p.67 Chapter 6 Splash Runtime Mechanisms p.69 6.1 Rate Control Mechanism p.69 6.2 Sensor Fusion Mechanism p.70 6.3 Mode Change Mechanism p.77 Chapter 7 Code Generation and Runtime System p.80 7.1 Build Unit-based Allocation p.80 7.2 Code Generation Template p.82 7.3 Splash Runtime System p.84 Chapter 8 Experimental Evaluation p.86 8.1 LKAS Program p.86 8.2 Experimental Environment p.91 8.3 Evaluating Rate Control p.92 8.4 Evaluating Sensor Fusion p.96 8.5 Evaluating Mode Change p.97 8.6 Evaluating Build Unit-based Allocation p.99 Chapter 9 Conclusion p.102 Bibliography p.104 Abstract in Korean p.113Docto

    Hard real-time performances in multiprocessor-embedded systems using ASMP-Linux

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    Multiprocessor systems, especially those based on multicore or multithreaded processors, and new operating system architectures can satisfy the ever increasing computational requirements of embedded systems.ASMP-LINUX is a modified, high responsiveness, open-source hard real-time operating system for multiprocessorsystems capable of providing high real-time performance while maintaining the code simple and not impacting on theperformances of the rest of the system. Moreover, ASMP-LINUX does not require code changing or application recompiling/relinking.In order to assess the performances of ASMP-LINUX, benchmarks have been performed on several hardware platformsand configurations

    Qduino: a cyber-physical programming platform for multicore Systems-on-Chip

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    Emerging multicore Systems-on-Chip are enabling new cyber-physical applications such as autonomous drones, driverless cars and smart manufacturing using web-connected 3D printers. Common to those applications is a communicating task pipeline, to acquire and process sensor data and produce outputs that control actuators. As a result, these applications usually have timing requirements for both individual tasks and task pipelines formed for sensor data processing and actuation. Current cyber-physical programming platforms, such as Arduino and embedded Linux with the POSIX interface do not allow application developers to specify those timing requirements. Moreover, none of them provide the programming interface to schedule tasks and map them to processor cores, while managing I/O in a predictable manner, on multicore hardware platforms. Hence, this thesis presents the Qduino programming platform. Qduino adopts the simplicity of the Arduino API, with additional support for real-time multithreaded sketches on multicore architectures. Qduino allows application developers to specify timing properties of individual tasks as well as task pipelines at the design stage. To this end, we propose a mathematical framework to derive each taskโ€™s budget and period from the specified end-to-end timing requirements. The second part of the thesis is motivated by the observation that at the center of these pipelines are tasks that typically require complex software support, such as sensor data fusion or image processing algorithms. These features are usually developed by many man-year engineering efforts and thus commonly seen on General-Purpose Operating Systems (GPOS). Therefore, in order to support modern, intelligent cyber-physical applications, we enhance the Qduino platformโ€™s extensibility by taking advantage of the Quest-V virtualized partitioning kernel. The platformโ€™s usability is demonstrated by building a novel web-connected 3D printer and a prototypical autonomous drone framework in Qduino

    The embedded Java benchmark suite JemBench

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    A TrustZone-assisted secure silicon on a co-design framework

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    Dissertaรงรฃo de mestrado em Engenharia Eletrรณnica Industrial e ComputadoresEmbedded systems were for a long time, single-purpose and closed systems, characterized by hardware resource constraints and real-time requirements. Nowadays, their functionality is ever-growing, coupled with an increasing complexity and heterogeneity. Embedded applications increasingly demand employment of general-purpose operating systems (GPOSs) to handle operator interfaces and general-purpose computing tasks, while simultaneously ensuring the strict timing requirements. Virtualization, which enables multiple operating systems (OSs) to run on top of the same hardware platform, is gaining momentum in the embedded systems arena, driven by the growing interest in consolidating and isolating multiple and heterogeneous environments. The penalties incurred by classic virtualization approaches is pushing research towards hardware-assisted solutions. Among the existing commercial off-the-shelf (COTS) technologies for virtualization, ARM TrustZone technology is gaining momentum due to the supremacy and lower cost of TrustZone-enabled processors. Programmable system-on-chips (SoCs) are becoming leading players in the embedded systems space, because the combination of a plethora of hard resources with programmable logic enables the efficient implementation of systems that perfectly fit the heterogeneous nature of embedded applications. Moreover, novel disruptive approaches make use of field-programmable gate array (FPGA) technology to enhance virtualization mechanisms. This masterโ€™s thesis proposes a hardware-software co-design framework for easing the economy of addressing the new generation of embedded systems requirements. ARM TrustZone is exploited to implement the root-of-trust of a virtualization-based architecture that allows the execution of a GPOS side-by-side with a real-time OS (RTOS). RTOS services were offloaded to hardware, so that it could present simultaneous improvements on performance and determinism. Instead of focusing in a concrete application, the goal is to provide a complete framework, specifically tailored for Zynq-base devices, that developers can use to accelerate a bunch of distinct applications across different embedded industries.Os sistemas embebidos foram, durante muitos anos, sistemas com um simples e รบnico propรณsito, caracterizados por recursos de hardware limitados e com cariz de tempo real. Hoje em dia, o nรบmero de funcionalidades comeรงa a escalar, assim como o grau de complexidade e heterogeneidade. As aplicaรงรตes embebidas exigem cada vez mais o uso de sistemas operativos (OSs) de uso geral (GPOS) para lidar com interfaces grรกficas e tarefas de computaรงรฃo de propรณsito geral. Porรฉm, os seus requisitos primordiais de tempo real mantรฉm-se. A virtualizaรงรฃo permite que vรกrios sistemas operativos sejam executados na mesma plataforma de hardware. Impulsionada pelo crescente interesse em consolidar e isolar ambientes mรบltiplos e heterogรฉneos, a virtualizaรงรฃo tem ganho uma crescente relevรขncia no domรญnio dos sistemas embebidos. As adversidades que advรฉm das abordagens de virtualizaรงรฃo clรกssicas estรฃo a direcionar estudos no รขmbito de soluรงรตes assistidas por hardware. Entre as tecnologias comerciais existentes, a tecnologia ARM TrustZone estรก a ganhar muita relevรขncia devido ร  supremacia e ao menor custo dos processadores que suportam esta tecnologia. Plataformas hibridas, que combinam processadores com lรณgica programรกvel, estรฃo em crescente penetraรงรฃo no domรญnio dos sistemas embebidos pois, disponibilizam um enorme conjunto de recursos que se adequam perfeitamente ร  natureza heterogรฉnea dos sistemas atuais. Alรฉm disso, existem soluรงรตes recentes que fazem uso da tecnologia de FPGA para melhorar os mecanismos de virtualizaรงรฃo. Esta dissertaรงรฃo propรตe uma framework baseada em hardware-software de modo a cumprir os requisitos da nova geraรงรฃo de sistemas embebidos. A tecnologia TrustZone รฉ explorada para implementar uma arquitetura que permite a execuรงรฃo de um GPOS lado-a-lado com um sistemas operativo de tempo real (RTOS). Os serviรงos disponibilizados pelo RTOS sรฃo migrados para hardware, para melhorar o desempenho e determinismo do OS. Em vez de focar numa aplicaรงรฃo concreta, o objetivo รฉ fornecer uma framework especificamente adaptada para dispositivos baseados em System-on-chips Zynq, de forma a que developers possam usar para acelerar um vasto nรบmero de aplicaรงรตes distintas em diferentes setores

    ElasticSimMATE: a Fast and Accurate gem5 Trace-Driven Simulator for Multicore Systems

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    International audienceMulticore system analysis requires efficient solutions for architectural parameter and scalability exploration. Long simulation time is the main drawback of current simulation approaches. In order to reduce the simulation time while keeping the accuracy levels, trace-driven simulation approaches have been developed. However, existing approaches do not allow multicore exploration or do not capture the behavior of multi-threaded programs. Based on the gem5 simulator, we developed a novel synchronization mechanism for multicore analysis based on the trace collection of synchronization events, instruction and dependencies. It allows efficient architectural parameter and scalability exploration with acceptable simulation speed and accuracy

    Bounding the End-to-End Execution Time in Distributed Real-Time Systems: Arguing the case for Deterministic Networks in Lingua Franca

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    Designing and implementing distributed systems with real-time requirements quickly reveal the complexity of handling time and logic across multiple systems. As data traverse a network, it is subjected to variable delay due to interfering traffic and variable load on network components. This introduces an element of non-determinism in execution time for distributed algorithms, which translates into increased error logic and pessimistic worst-case estimates. Over the next few years, it is expected that Cyber-Physical Systems will see many new use cases, and the network connecting these will play an ever more important role. Combined with the onset of the fourth industrial revolution, IEEEs Time Sensitive Networking, IETFs Deterministic Networking, and 3GPPs Ultra Reliable Low Latency profile will play a vital role in realizing these systems. Coordination languages such as Lingua Franca can offer a substantial contribution to the design process and implementation of distributed systems such as Cyber-Phyiscal Systems, both through its model of computation which elevates time to a first-class citizen and with its support for distributed models. In this paper, we show that by introducing deterministic network channels with a fixed delay, the worst-case execution time is not increased whereas the variance in total execution time from start to finish is greatly reduced. For a coordination language such as LF, this means that we can analyze a system using much tighter delay bounds for network traffic, which in turn can yield better resource utilization.publishedVersio

    pioman: a pthread-based Multithreaded Communication Engine

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    International audienceRecent cluster architectures include dozens of cores per node, with all cores sharing the network resources. To program such architectures, hybrid models mixing MPI+threads, and in particular MPI+OpenMP are gaining popularity. This imposes new requirements on communication libraries, such as the need for MPI_THREAD_MULTIPLE level of multi-threading support. Moreover, the high number of cores brings new op-portunities to parallelize communication libraries, so as to have proper background progression of communication and commu-nication/computation overlap. In this paper, we present pioman, a generic framework to be used by MPI implementations, that brings seamless asynchronous progression of communication by opportunistically using available cores. It uses system threads and thus is composable with any runtime system used for multithreading. Through various benchmarks, we demonstrate that our pioman-based MPI implementation exhibits very good properties regarding overlap, progression, and multithreading, and outperforms state-of-art MPI implementations

    Satisfying hard real-time constraints using COTS components

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    L'utilizzo di componenti COTS (Commercial-Off-The-Shelf) รจ sempre piรน comune nella produzione di sistemi embedded real-time. Prodotti commerciali, come periferiche di Input/Output e bus di sistema, vengono utilizzati in sistemi real-time al fine di ridurre i costi, il tempo di produzione, ed aumentare le performance. Sfortunatamente, hardware e sistemi operativi COTS sono progettati principalmente per ottimizzare le performance, ma con poca attenzione verso determinismo, predicibilitร  ed affidabilitร . Per questa ragione, molte problematiche devono ancora essere affrontate prima di un loro impiego in sistemi real-time ad alta criticita'. In questa tesi abbiamo centrato la nostra attenzione su alcune delle piu' importanti sorgenti di impredicibilita' che devono essere rimosse al fine di integrare hardware e software COTS in sistemi hard real-time. Come prima cosa abbiamo sviluppato ASMP-Linux, una variante di Linux che minimizza overhead e latenza del sistema operativo. Successivamente abbiamo progettato ed implementato un nuovo sistema di gestione dell'I/O, basato sul Real-Time Bridge, un nuovo componente hardware che fornisce isolamento temporale sui bus COTS e rimuove le interferenze fra periferiche di I/O. E' stato anche sviluppato un Multi-Flow Real-Time Bridge per assicurare predicibilita' nel caso di periferiche condivise. Infine abbiamo proposto PREM, un nuovo modello di esecuzione per sistemi real-time che elimina le interferenze fra periferiche e CPU, e quelle fra processi ad alta criticita' ed interruzioni hardware. Per ognuna delle nostre soluzioni saranno descritti in dettaglio gli aspetti teorici, l'implementazione dei prototipi ed i risultati sperimentali.Real-time embedded systems are increasingly being built using Commercial Off-The-Shelf (COTS) components such as mass-produced peripherals and buses to reduce costs, time-to-market, and increase performance. Unfortunately, COTS hardware and operating systems are typically designed to optimize average performance, instead of determinism, predictability, and reliability, hence their employment in high criticality real-time systems is still a daunting task. In this thesis, we addressed some of the most important sources of unpredictability which must be removed in order to integrate COTS hardware and software into hard real-time systems. We first developed ASMP-Linux, a variant of Linux, capable of minimizing both operating system overhead and latency. Next, we designed and implemented a new I/O management system, based on real-time bridges, a novel hardware component that provides temporal isolation on the COTS bus and removes the interference among I/O peripherals. A multi-flow real-time bridge has been also developed to address interperipheral interference, allowing predictable device sharing. Finally, we propose PREM, a new execution model for real-time systems which eliminates interference between peripherals and the CPU, as well as interference between a critical task and driver interrupts. For each of our solutions, we will describe in detail theory aspects, as well as prototype implementations and experimental measurements
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