Electronic measurement and control of spin transport in Silicon

The electron spin lifetime and diffusion length are transport parameters that define the scale of coherence in spintronic devices and circuits. Since these parameters are many orders of magnitude larger in semiconductors than in metals, semiconductors could be the most suitable for spintronics. Thus far, spin transport has only been measured in direct-bandgap semiconductors or in combination with magnetic semiconductors, excluding a wide range of non-magnetic semiconductors with indirect bandgaps. Most notable in this group is silicon (Si), which (in addition to its market entrenchment in electronics) has long been predicted a superior semiconductor for spintronics with enhanced lifetime and diffusion length due to low spin-orbit scattering and lattice inversion symmetry. Despite its exciting promise, a demonstration of coherent spin transport in Si has remained elusive, because most experiments focused on magnetoresistive devices; these methods fail because of universal impedance mismatch obstacles, and are obscured by Lorentz magnetoresistance and Hall effects. Here we demonstrate conduction band spin transport across 10 microns undoped Si, by using spin-dependent ballistic hot-electron filtering through ferromagnetic thin films for both spin-injection and detection. Not based on magnetoresistance, the hot electron spin-injection and detection avoids impedance mismatch issues and prevents interference from parasitic effects. The clean collector current thus shows independent magnetic and electrical control of spin precession and confirms spin coherent drift in the conduction band of silicon.Comment: Single PDF file with 4 Figure

Optical Phonon Limited High Field Transport in Layered Materials

An optical phonon limited velocity model has been employed to investigate high-field transport in a selection of layered 2D materials for both, low-power logic switches with scaled supply voltages, and high-power, high-frequency transistors. Drain currents, effective electron velocities and intrinsic cut-off frequencies as a function of carrier density have been predicted thus providing a benchmark for the optical phonon limited high-field performance limits of these materials. The optical phonon limited carrier velocities of a selection of transition metal dichalcogenides and black phosphorus are found to be modest as compared to their n-channel silicon counterparts, questioning the utility of these devices in the source-injection dominated regime. h-BN, at the other end of the spectrum, is shown to be a very promising material for high-frequency high-power devices, subject to experimental realization of high carrier densities, primarily due to its large optical phonon energy. Experimentally extracted saturation velocities from few-layer MoS2 devices show reasonable qualitative and quantitative agreement with predicted values. Temperature dependence of measured vsat is discussed and found to fit a velocity saturation model with a single material dependent fit parameter.Comment: 8 pages, 6 figure

Silicon-CMOS Compatible In-Situ CCVD Grown Graphene Transistors with Ultra-High On/Off-Current Ratio

By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1E7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.Comment: 16 pages, 4 figure

Electron Mobility and Magneto Transport Study of Ultra-Thin Channel Double-Gate Si MOSFETs

We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range 7-17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/Vs, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing