HDL optimization using timed decision table

Abstract System-level presynthesis refers to the optimization of an input HDL description that produces an optimized HDL description suitable for subsequent synthesis tasks. In this paper, we present optimization of control ow i n behavioral HDL descriptions using external Don't Care conditions. The optimizations are carried out using a tabular model of system functionality, called Timed Decisio

Decomposition of timed decision tables and its use in presynthesis optimizations

In this paper we introduce the decomposition of Timed Decision Tables (TDT), a tabular model of system behavior. The decomposition can be used in system partitioning or in HDL code restructuring to improve synthesis results. The TDT decomposition is based on the kernel extraction algorithm. By experimenting using named benchmarks, we demonstrate how TDT decomposition can be used in presynthesis optimizations. Presynthesis optimizations transform a behavioral HDL description into optimized HDL description that results in improved synthesized circuits

Decomposition of Timed Decision Tables and its Use in Presynthesis Optimizations

In this paper we introduce the decomposition of Timed Decision Tables (TDT), a tabular model of system behavior. The decomposition can be used in system partitioning or in HDL code restructuring to improve synthesis results. The TDT decomposition is based on the kernel extraction algorithm. By experimenting using named benchmarks, we demonstrate how TDT decomposition can be used in presynthesis optimizations. Presynthesis optimizations transform a behavioral HDL description into optimized HDL description that results in improved synthesized circuits

System modeling and presynthesis using timed decision tables

In this paper, we present a tabular model of system behavior called Timed Decision Table (TDT). The TDT model is useful for identifying control-data interaction and in performing control-oriented optimizations. TDTs provide an ideal vehicle to implement source-level optimizations on a given behavioral description in a procedural hardware description language (HDL). These optimizations are used to produce improved synthesis results by simplifying the HDL models using Don't Cares or assertions in particular.TDT also provides a convenient data structure for extracting information that can be used in further synthesis subtasks to obtain improved synthesis results. One example of this is the information on mutual exclusiveness between a pair of operations, which can be used to optimize operation scheduling.Source-level control-flow optimization and analysis which extracts useful information from input HDL source for optimization in synthesis process are collectively referred to as presynthesis. We have implemented TDT-based presynthesis techniques in a program called PUMPKIN. Our experiments running PUMPKIN on named benchmarks shows improved synthesis results after presynthesis has been carried out on the input HDL descriptions and information extracted in presynthesis has been incorporated in the synthesis optimizations