Electronic and spintronic transport in germanium nanostructures

textThe digital information processing system has benefited tremendously from the invention and development of complementary metal-oxide-semiconductor (CMOS) integrated circuits. The relentless scaling of the physical dimensions of transistors has been consistently delivering improved overall circuit density and performance every technology generation. However, the continuation of this trend is in question for silicon-based transistors when quantum mechanical tunneling becomes more relevant; further scaling in feature sizes can lead to increased leakage current and power dissipation. Numerous research efforts have been implemented to address these scaling challenges, either by aiming to increase the performance at the transistor level or to introduce new functionalities at the circuit level. In the first approach, novel materials and device structures are explored to improve the performance of CMOS transistors, including the use of high-mobility materials (e.g. III-V compounds and germanium) as the channel, and multi-gate structures. On the other hand, the overall circuit capability could be increased if other state variables are exploited in the electronic devices, such as the electron spin degree of freedom (e.g. spintronics). Here we explore the potential of germanium nanowires in both CMOS and beyond-CMOS applications, studying the electronic and spintronic transport in this material system. Germanium is an attractive replacement to silicon as the channel material in CMOS technology, thanks to its lighter effective electron and hole mass. The nanowire structures, directly synthesized using chemical vapor deposition, provide a natural platform for multi-gate structures in which the electrostatic control of the gate is enhanced. We present the realization and scaling properties of germanium-silicon-germanium core-shell nanowire n-type, [omega]-gate field-effect transistors (FETs). By studying the channel length dependence of NW FET characteristics, we conclude that the intrinsic channel resistance is the main limiting factor of the drive current of Ge NW n-FETs. Utilizing the electron spins in semiconductor devices can in principle enhance overall circuit performance and functionalities. Electrical injection of spin-polarized electrons into a semiconductor, large spin diffusion length, and an integration friendly platform are desirable ingredients for spin based-devices. Here we demonstrate lateral spin injection and detection in Ge NWs, by using ferromagnetic metal contacts and tunnel barriers for contact resistance engineering. We map out the contact resistance window for which spin transport is observed, manifestly showing the conductivity matching required for spin injection.Electrical and Computer Engineerin

Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications

Transport properties and low-frequency noise in low-dimensional structures

Les propriétés électriques et physiques de structures à faible dimensionalité ont été étudiées pour des applications dans des domaines divers comme l électronique, les capteurs. La mesure du bruit bruit à basse fréquence est un outil très utile pour obtenir des informations relatives à la dynamique des porteurs, au piègeage des charges ou aux mécanismes de collision. Dans cette thèse, le transport électronique et le bruit basse fréquence mesurés dans des structures à faible dimensionnalité comme les dispositifs multi-grilles (FinFET, JLT ), les nanofils 3D en Si/SiGe, les nanotubes de carbone ou à base de graphène sont présentés. Pour les approches top-down et bottom-up , l impact du bruit est analysé en fonction de la dimensionalité, du type de conduction (volume vs surface), de la contrainte mécanique et de la présence de jonction metal-semiconducteur.Electrical and physical properties of low-dimensional structures have been studied for the various applications such as electronics, sensors, and etc. Low-frequency noise measurement is also a useful technique to give more information for the carrier dynamics correlated to the oxide traps, channel defects, and scattering. In this thesis, the electrical transport and low-frequency noise of low-dimensional structure devices such as multi-gate structures (e.g. FinFETs and Junctionless FETs), 3-D stacked Si/SiGe nanowire FETs, carbon nanotubes, and graphene are presented. From the view point of top-down and bottom-up approaches, the impacts of LF noise are investigated according to the dimensionality, conduction mechanism (surface or volume conduction), strain technique, and metal-semiconductor junctions.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Studies of short channel effects and Performance enhancement of nano-mosfet Based on multi-objective genetic algorithm Approach

The nano-scale devices face a major issue i.e Short Channel Effects, as a result of which the performance of the devices degrade. To enhance the performance of such devices, the SCEs should be reduced. This thesis contributes to enhance the performance of nano-scaled DG MOSFET by re-ducing the short channel effects. To approach towards the main objective of the thesis, a study has been done on analytical modeling of undoped symmetric DG MOSFET. Then, to get the picture of SCEs, the electrical parameters such as maximum Drain current(Ion),Leakage current(Ioff ), Sub threshold Swing (SS), Threshold voltage (Vth ), and Drain In-duced Barrier Lowering (DIBL) are analytically derived by solving 2-dimensional Poisson’s equation and the same are studied with the variation of design parameters such as L, tsi and tox. To validate such analytical models, SCEs are studied using ATLAS device simulator. Graded Cannel engineering techniques are used for reduction of SCEs. For further reduction or minimization of SCEs, a multi-objective optimization technique is used to enhance the accuracy with optimum design parameters. To validate the optimized structure, a simulated model is built with those optimized values of the design parameter and the performance of the device is compared with the existing result [32]

Modeling & Performance Enhancement Analysis of Some Nanoscale MOSFET Structures

Silicon-on-Insulator (SOI) has been the forerunner of the CMOS technology in the last few decades offering superior CMOS devices with higher speed, higher density and reduced second order effects for submicron VLSI applications. Recent experimental studies invigorated interest in Fully Depleted (FD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. Various new structures with different engineering concepts have been reported to reduce the SCEs in SOI platform. Among them Strain engineering and high-k gate dielectric with metal gate technology are very popular for enhancing the carrier mobility and reduction of gate leakage current. In this thesis, first physics based 2-D model for surface potential, threshold voltage and electric field for a Fully Depleted Strained Silicon on Insulator (FD-S-SOI) MOSFET by solving the two dimensional Poisson’s equation is presented. The model details the role of various MOS parameters like germanium concentration, body doping concentration, strained silicon thickness, oxide thickness and gate metal work function influencing the surface potential, threshold voltage and electric field. Then extensive numerical simulation is done to study the effect of device design engineering on the analog/RF performance of nanoscale DGMOSFET by varying the gate work function, channel length and gate oxide. Including the Short Channel Effects (SCEs) the important analog/RF figures of merit (FOMs) are also examined. Finally one optimum device is presented with great immunization to SCEs and highly applicable to analog/RF applications

Function Implementation in a Multi-Gate Junctionless FET Structure

Title from PDF of title page, viewed September 18, 2023Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (pages 95-117)Dissertation (Ph.D.)--Department of Computer Science and Electrical Engineering, Department of Physics and Astronomy. University of Missouri--Kansas City, 2023This dissertation explores designing and implementing a multi-gate junctionless field-effect transistor (JLFET) structure and its potential applications beyond conventional devices. The JLFET is a promising alternative to conventional transistors due to its simplified fabrication process and improved electrical characteristics. However, previous research has focused primarily on the device's performance at the individual transistor level, neglecting its potential for implementing complex functions. This dissertation fills this research gap by investigating the function implementation capabilities of the JLFET structure and proposing novel circuit designs based on this technology. The first part of this dissertation presents a comprehensive review of the existing literature on JLFETs, including their fabrication techniques, operating principles, and performance metrics. It highlights the advantages of JLFETs over traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) and discusses the challenges associated with their implementation. Additionally, the review explores the limitations of conventional transistor technologies, emphasizing the need for exploring alternative device architectures. Building upon the theoretical foundation, the dissertation presents a detailed analysis of the multi-gate JLFET structure and its potential for realizing advanced functions. The study explores the impact of different design parameters, such as channel length, gate oxide thickness, and doping profiles, on the device performance. It investigates the trade-offs between power consumption, speed, and noise immunity, and proposes design guidelines for optimizing the function implementation capabilities of the JLFET. To demonstrate the practical applicability of the JLFET structure, this dissertation introduces several novel circuit designs based on this technology. These designs leverage the unique characteristics of the JLFET, such as its steep subthreshold slope and improved on/off current ratio, to implement complex functions efficiently. The proposed circuits include arithmetic units, memory cells, and digital logic gates. Detailed simulations and analyses are conducted to evaluate their performance, power consumption, and scalability. Furthermore, this dissertation explores the potential of the JLFET structure for emerging technologies, such as neuromorphic computing and bioelectronics. It investigates how the JLFET can be employed to realize energy-efficient and biocompatible devices for applications in artificial intelligence and biomedical engineering. The study investigates the compatibility of the JLFET with various materials and substrates, as well as its integration with other functional components. In conclusion, this dissertation contributes to the field of nanoelectronics by providing a comprehensive investigation into the function implementation capabilities of the multi-gate JLFET structure. It highlights the potential of this device beyond its individual transistor performance and proposes novel circuit designs based on this technology. The findings of this research pave the way for the development of advanced electronic systems that are more energy-efficient, faster, and compatible with emerging applications in diverse fields.Introduction -- Literature review -- Crosstalk principle -- Experiment of crosstalk -- Device architecture -- Simulation & results -- Conclusio

Silicon Nanodevices

This book is a collection of scientific articles which brings research in Si nanodevices, device processing, and materials. The content is oriented to optoelectronics with a core in electronics and photonics. The issue of current technology developments in the nanodevices towards 3D integration and an emerging of the electronics and photonics as an ultimate goal in nanotechnology in the future is presented. The book contains a few review articles to update the knowledge in Si-based devices and followed by processing of advanced nano-scale transistors. Furthermore, material growth and manufacturing of several types of devices are presented. The subjects are carefully chosen to critically cover the scientific issues for scientists and doctoral students

Two dimensional quantum and reliability modelling for lightly doped nanoscale devices

The downscaling of MOSFET devices leads to well-studied short channel effects and more complex quantum mechanical effects. Both quantum and short channel effects not only alter the performance but they also affect the reliability. This continued scaling of the MOS device gate length puts a demand on the reduction of the gate oxide thickness and the substrate doping density. Quantum mechanical effects give rise to the quantization of energy in the conduction band, which consequently creates a larger effective bandgap and brings a displacement of the inversion layer charge out of the Si/SiO2 interface. Such a displacement of charge is equivalent to an increase in the effective oxide layer thickness, a growth in the threshold voltage, and a decrease in the current level. Therefore, using the classical analysis approach without including the quantum effects may lead to perceptible errors in the prognosis of the performance of modern deep submicron devices. In this work, compact Verilog-A compatible 2D models including quantum short channel effects and confinement for the potential, threshold voltage, and the carrier charge sheet density for symmetrical lightly doped double-gate MOSFETs are developed. The proposed models are not only applicable to ultra-scaled devices but they have also been derived from analytical 2D Poisson and 1D Schrodinger equations including 2D electrostatics, in order to incorporate quantum mechanical effects. Electron and hole quasi-Fermi potential effects were considered. The models were further enhanced to include negative bias temperature instability (NBTI) in order to assess the reliability of the device. NBTI effects incorporated into the models constitute interface state generation and hole-trapping. The models are continuous and have been verified by comparison with COMSOL and BALMOS numerical simulations for channel lengths down to 7nm; very good agreement within ±5% has been observed for silicon thicknesses ranging from 3nm to 20nm at 1 GHz operation after 10 years