91 research outputs found
HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation
Testing an integrated circuit (IC) is a highly compute-intensive process. For
today's complex designs, tests for many hard-to-detect faults are typically
generated using deterministic test generation (DTG) algorithms. Machine
Learning (ML) is being increasingly used to increase the test coverage and
decrease the overall testing time. Such proposals primarily reduce the wasted
work in the classic Path Oriented Decision Making (PODEM) algorithm without
compromising on the test quality. With variants of PODEM, many times there is a
need to backtrack because further progress cannot be made. There is thus a need
to predict the best strategy at different points in the execution of the
algorithm. The novel contribution of this paper is a 2-level predictor: the top
level is a meta predictor that chooses one of several predictors at the lower
level. We choose the best predictor given a circuit and a target net. The
accuracy of the top-level meta predictor was found to be 99\%. This leads to a
significantly reduced number of backtracking decisions compared to
state-of-the-art ML-based and conventional solutions. As compared to a popular,
state-of-the-art commercial ATPG tool, our 2-level predictor (HybMT) shows an
overall reduction of 32.6\% in the CPU time without compromising on the fault
coverage for the EPFL benchmark circuits. HybMT also shows a speedup of 24.4\%
and 95.5\% over the existing state-of-the-art (the baseline) while obtaining
equal or better fault coverage for the ISCAS'85 and EPFL benchmark circuits,
respectively.Comment: 9 pages, 7 figures and 7 tables. Changes from the previous version:
We performed more experiments with different regressor models and also
proposed a new neural network model, HybNN. We report the results for the
EPFL benchmark circuits (most recent and large) and compare our results
against a popular commercial ATPG too
A Comprehensive Test Pattern Generation Approach Exploiting SAT Attack for Logic Locking
The need for reducing manufacturing defect escape in today's safety-critical
applications requires increased fault coverage. However, generating a test set
using commercial automatic test pattern generation (ATPG) tools that lead to
zero-defect escape is still an open problem. It is challenging to detect all
stuck-at faults to reach 100% fault coverage. In parallel, the hardware
security community has been actively involved in developing solutions for logic
locking to prevent IP piracy. Locks (e.g., XOR gates) are inserted in different
locations of the netlist so that an adversary cannot determine the secret key.
Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in
[1], can break different logic locking schemes in minutes. In this paper, we
propose a novel test pattern generation approach using the powerful SAT attack
on logic locking. A stuck-at fault is modeled as a locked gate with a secret
key. Our modeling of stuck-at faults preserves the property of fault activation
and propagation. We show that the input pattern that determines the key is a
test for the stuck-at fault. We propose two different approaches for test
pattern generation. First, a single stuck-at fault is targeted, and a
corresponding locked circuit with one key bit is created. This approach
generates one test pattern per fault. Second, we consider a group of faults and
convert the circuit to its locked version with multiple key bits. The inputs
obtained from the SAT tool are the test set for detecting this group of faults.
Our approach is able to find test patterns for hard-to-detect faults that were
previously failed in commercial ATPG tools. The proposed test pattern
generation approach can efficiently detect redundant faults present in a
circuit. We demonstrate the effectiveness of the approach on ITC'99 benchmarks.
The results show that we can achieve a perfect fault coverage reaching 100%.Comment: 12 pages, 7 figures, 5 table
Efficient Path Delay Test Generation with Boolean Satisfiability
This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver.
Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure
Test Generation Based on CLP
Functional ATPGs based on simulation are fast,
but generally, they are unable to cover corner cases, and
they cannot prove untestability. On the contrary, functional
ATPGs exploiting formal methods, being exhaustive,
cover corner cases, but they tend to suffer of the state
explosion problem when adopted for verifying large designs.
In this context, we have defined a functional ATPG
that relies on the joint use of pseudo-deterministic simulation
and Constraint Logic Programming (CLP), to
generate high-quality test sequences for solving complex
problems. Thus, the advantages of both simulation-based
and static-based verification techniques are preserved, while
their respective drawbacks are limited. In particular, CLP,
a form of constraint programming in which logic programming
is extended to include concepts from constraint satisfaction,
is well-suited to be jointly used with simulation. In
fact, information learned during design exploration by simulation
can be effectively exploited for guiding the search of
a CLP solver towards DUV areas not covered yet. The test
generation procedure relies on constraint logic programming
(CLP) techniques in different phases of the test generation
procedure.
The ATPG framework is composed of three functional
ATPG engines working on three different models of the
same DUV: the hardware description language (HDL)
model of the DUV, a set of concurrent EFSMs extracted
from the HDL description, and a set of logic constraints
modeling the EFSMs. The EFSM paradigm has been selected
since it allows a compact representation of the DUV
state space that limits the state explosion problem typical
of more traditional FSMs. The first engine is randombased,
the second is transition-oriented, while the last is
fault-oriented.
The test generation is guided by means of transition coverage and fault coverage. In particular, 100% transition
coverage is desired as a necessary condition for fault
detection, while the bit coverage functional fault model
is used to evaluate the effectiveness of the generated test
patterns by measuring the related fault coverage.
A random engine is first used to explore the DUV state
space by performing a simulation-based random walk. This
allows us to quickly fire easy-to-traverse (ETT) transitions
and, consequently, to quickly cover easy-to-detect (ETD)
faults. However, the majority of hard-to-traverse (HTT)
transitions remain, generally, uncovered.
Thus, a transition-oriented engine is applied to
cover the remaining HTT transitions by exploiting a
learning/backjumping-based strategy.
The ATPG works on a special kind of EFSM, called
SSEFSM, whose transitions present the most uniformly
distributed probability of being activated and can be effectively
integrated to CLP, since it allows the ATPG to invoke
the constraint solver when moving between EFSM states.
A constraint logic programming-based (CLP) strategy is
adopted to deterministically generate test vectors that satisfy
the guard of the EFSM transitions selected to be traversed. Given a transition of the SSEFSM, the solver
is required to generate opportune values for PIs that enable
the SSEFSM to move across such a transition.
Moreover, backjumping, also known as nonchronological
backtracking, is a special kind of backtracking
strategy which rollbacks from an unsuccessful
situation directly to the cause of the failure. Thus,
the transition-oriented engine deterministically backjumps
to the source of failure when a transition, whose guard
depends on previously set registers, cannot be traversed.
Next it modifies the EFSM configuration to satisfy the
condition on registers and successfully comes back to the
target state to activate the transition.
The transition-oriented engine generally allows us to
achieve 100% transition coverage. However, 100% transition
coverage does not guarantee to explore all DUV corner
cases, thus some hard-to-detect (HTD) faults can escape
detection preventing the achievement of 100% fault coverage.
Therefore, the CLP-based fault-oriented engine is finally
applied to focus on the remaining HTD faults.
The CLP solver is used to deterministically search for
sequences that propagate the HTD faults observed, but not
detected, by the random and the transition-oriented engine.
The fault-oriented engine needs a CLP-based representation
of the DUV, and some searching functions to generate
test sequences. The CLP-based representation is automatically
derived from the S2EFSM models according to the
defined rules, which follow the syntax of the ECLiPSe CLP
solver. This is not a trivial task, since modeling the
evolution in time of an EFSM by using logic constraints
is really different with respect to model the same behavior
by means of a traditional HW description language. At
first, the concept of time steps is introduced, required to
model the SSEFSM evolution through the time via CLP.
Then, this study deals with modeling of logical variables
and constraints to represent enabling functions and update
functions of the SSEFSM.
Formal tools that exhaustively search for a solution frequently
run out of resources when the state space to be analyzed
is too large. The same happens for the CLP solver,
when it is asked to find a propagation sequence on large sequential
designs. Therefore we have defined a set of strategies
that allow to prune the search space and to manage the
complexity problem for the solver
Optimizing Test Pattern Generation Using Top-Off ATPG Methodology for Stuck–AT, Transition and Small Delay Defect Faults
The ever increasing complexity and size of digital circuits complemented by Deep Sub Micron (DSM) technology trends today pose challenges to the efficient Design For Test (DFT) methodologies. Innovation is required not only in designing the digital circuits, but also in automatic test pattern generation (ATPG) to ensure that the pattern set screens all the targeted faults while still complying with the Automatic Test Equipment (ATE) memory constraints.
DSM technology trends push the requirements of ATPG to not only include the conventional static defects but also to include test patterns for dynamic defects. The current industry practices consider test pattern generation for transition faults to screen dynamic defects. It has been observed that just screening for transition faults alone is not sufficient in light of the continuing DSM technology trends. Shrinking technology nodes have pushed DFT engineers to include Small Delay Defect (SDD) test patterns in the production flow. The current industry standard ATPG tools are evolving and SDD ATPG is not the most economical option in terms of both test generation CPU time and pattern volume. New techniques must be explored in order to ensure that a quality test pattern set can be generated which includes patterns for stuck-at, transition and SDD faults, all the while ensuring that the pattern volume remains economical.
This thesis explores the use of a “Top-Off” ATPG methodology to generate an optimal test pattern set which can effectively screen the required fault models while containing the pattern volume within a reasonable limit
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