Millimeter-wave Wireless LAN and its Extension toward 5G Heterogeneous Networks

Millimeter-wave (mmw) frequency bands, especially 60 GHz unlicensed band, are considered as a promising solution for gigabit short range wireless communication systems. IEEE standard 802.11ad, also known as WiGig, is standardized for the usage of the 60 GHz unlicensed band for wireless local area networks (WLANs). By using this mmw WLAN, multi-Gbps rate can be achieved to support bandwidth-intensive multimedia applications. Exhaustive search along with beamforming (BF) is usually used to overcome 60 GHz channel propagation loss and accomplish data transmissions in such mmw WLANs. Because of its short range transmission with a high susceptibility to path blocking, multiple number of mmw access points (APs) should be used to fully cover a typical target environment for future high capacity multi-Gbps WLANs. Therefore, coordination among mmw APs is highly needed to overcome packet collisions resulting from un-coordinated exhaustive search BF and to increase the total capacity of mmw WLANs. In this paper, we firstly give the current status of mmw WLANs with our developed WiGig AP prototype. Then, we highlight the great need for coordinated transmissions among mmw APs as a key enabler for future high capacity mmw WLANs. Two different types of coordinated mmw WLAN architecture are introduced. One is the distributed antenna type architecture to realize centralized coordination, while the other is an autonomous coordination with the assistance of legacy Wi-Fi signaling. Moreover, two heterogeneous network (HetNet) architectures are also introduced to efficiently extend the coordinated mmw WLANs to be used for future 5th Generation (5G) cellular networks.Comment: 18 pages, 24 figures, accepted, invited paper

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin

Introduction to the Issue on Hybrid Analog-Digital Signal Processing for Hardware-Efficient Large-Scale Antenna Arrays (Part I)

The papers in this special section focus on hybrid analog-digital signal processing for hardware efficient large scale antenna arrays. Hybrid analog-digital (HAD) processing provides a key technology for the coming generations of wireless networks, as a means of obtaining hardware-efficient transceivers. The principle behind HAD is that the transceiver processing is divided into the analog and digital domain, where networks of analog components implement large-dimensional processing at the transceiver front end, allowing for a low-dimensional digital processing which necessitates only a few RF chains. This technology has recently been brought at the forefront of research motivated by the proliferation of millimeter-wave (mmWave) communications, as a solution to circumvent the use of large numbers of expensive mmWave RF components. Its scope however is not limited solely tommWave, as hardwareefficient transmission is key for small cell deployments in the microwave frequencies and also in emerging applications such as the internet of things (IoT) involving massive connectivity. All these applications still rely on transceivers capable of beamforming, using cheap, low-power, and physically small devices. Accordingly, the aim of this Special Issue (SI) has been to gather the relevant contributions focusing on the practical challenges of hybrid analog-digital transmission

Total Cost of Ownership of Digital vs. Analog Radio-Over-Fiber Architectures for 5G Fronthauling

The article analyzes the total cost of ownership (TCO) of 5G fronthauling solutions based on analog and digital radio-over-fiber (RoF) architectures in cloud radio access networks (C-RANs). The capital and operational expenditures (CAPEX, OPEX) are assessed, for a 10-year period, considering three different RoF techniques: intermediate frequency analog RoF (IF-A-RoF), digital signal processing (DSP) assisted analog RoF (DSP-A-RoF), and digital RoF (D-RoF) based on the common public radio interface (CPRI) specifications. The greenfield deployment scenario under exam includes both fiber trenching (FT) and fiber leasing (FL) options. The TCO is assessed while varying (i) the number of aggregated subcarriers, (ii) the number of three-sector antennas located at the base station, and (iii) the mean fiber-hop length. The comparison highlights the significance that subcarrier aggregation has on the cost efficiency of the analog RoF solutions. In addition, the analysis details the contribution of each cost category to the overall CAPEX and OPEX values. The obtained results indicate that subcarrier aggregation via DSP results in high cost efficiency for a mobile fronthaul network, while a CPRI-based architecture together with FL brings the highest OPEX value

Full-Duplex Wireless for 6G: Progress Brings New Opportunities and Challenges

The use of in-band full-duplex (FD) enables nodes to simultaneously transmit and receive on the same frequency band, which challenges the traditional assumption in wireless network design. The full-duplex capability enhances spectral efficiency and decreases latency, which are two key drivers pushing the performance expectations of next-generation mobile networks. In less than ten years, in-band FD has advanced from being demonstrated in research labs to being implemented in standards and products, presenting new opportunities to utilize its foundational concepts. Some of the most significant opportunities include using FD to enable wireless networks to sense the physical environment, integrate sensing and communication applications, develop integrated access and backhaul solutions, and work with smart signal propagation environments powered by reconfigurable intelligent surfaces. However, these new opportunities also come with new challenges for large-scale commercial deployment of FD technology, such as managing self-interference, combating cross-link interference in multi-cell networks, and coexistence of dynamic time division duplex, subband FD and FD networks.Comment: 21 pages, 15 figures, accepted to an IEEE Journa

Full-duplex wireless communications: challenges, solutions and future research directions

The family of conventional half-duplex (HD) wireless systems relied on transmitting and receiving in different time-slots or frequency sub-bands. Hence the wireless research community aspires to conceive full-duplex (FD) operation for supporting concurrent transmission and reception in a single time/frequency channel, which would improve the attainable spectral efficiency by a factor of two. The main challenge encountered in implementing an FD wireless device is the large power difference between the self-interference (SI) imposed by the device’s own transmissions and the signal of interest received from a remote source. In this survey, we present a comprehensive list of the potential FD techniques and highlight their pros and cons. We classify the SI cancellation techniques into three categories, namely passive suppression, analog cancellation and digital cancellation, with the advantages and disadvantages of each technique compared. Specifically, we analyse the main impairments (e.g. phase noise, power amplifier nonlinearity as well as in-phase and quadrature-phase (I/Q) imbalance, etc.) that degrading the SI cancellation. We then discuss the FD based Media Access Control (MAC)-layer protocol design for the sake of addressing some of the critical issues, such as the problem of hidden terminals, the resultant end-to-end delay and the high packet loss ratio (PLR) due to network congestion. After elaborating on a variety of physical/MAC-layer techniques, we discuss potential solutions conceived for meeting the challenges imposed by the aforementioned techniques. Furthermore, we also discuss a range of critical issues related to the implementation, performance enhancement and optimization of FD systems, including important topics such as hybrid FD/HD scheme, optimal relay selection and optimal power allocation, etc. Finally, a variety of new directions and open problems associated with FD technology are pointed out. Our hope is that this treatise will stimulate future research efforts in the emerging field of FD communication

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios