Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

Frequency compensation of CMOS operational amplifier.

Ho Kin-Pui.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 92-95).Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.4Acknowledgements --- p.5Table of Contents --- p.6List of Figures --- p.10List of Tables --- p.14Chapter Chapter 1 --- Introduction --- p.15Overview --- p.15Objective --- p.17Thesis Organization --- p.17Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19Chapter 2.1.1 --- Input Differential Voltage Range --- p.19Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20Chapter 2.1.4 --- Input Offset Voltage --- p.20Chapter 2.1.5 --- Gain Bandwidth Product --- p.21Chapter 2.1.6 --- Phase Margin --- p.22Chapter 2.1.7 --- Slew Rate --- p.22Chapter 2.1.8 --- Settling Time --- p.23Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24Chapter 2.2.1 --- Overview --- p.24Chapter 2.2.2 --- Miller Compensation --- p.25Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27Chapter 3.1 --- Introduction --- p.27Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28Chapter 3.2.1 --- Circuit Description --- p.29Chapter 3.2.2 --- Small Signal analysis --- p.32Chapter 3.2.3 --- Simulation Results --- p.34Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38Chapter 4.1 --- Introduction --- p.38Chapter 4.2 --- Frequency Response --- p.39Chapter 4.2.1 --- Gain-bandwidth product --- p.40Chapter 4.2.2 --- Right half complex plane zero --- p.40Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42Chapter 4.3 --- Components Sizing --- p.47Chapter 4.4 --- Circuit Simulation --- p.48Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Working principle of the proposed circuit --- p.54Chapter 5.2.1 --- The introduction of nulling resistor --- p.55Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55Chapter 5.2.3 --- Small Signal Analysis --- p.57Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60Chapter 5.2.6 --- Stability Conditions --- p.63Chapter 5.3 --- Performance Comparison --- p.67Chapter 5.4 --- Conclusion: --- p.70Chapter 5.4.1 --- Circuit Modifications: --- p.70Chapter 5.4.2 --- Advantages: --- p.71Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72Chapter 6.1 --- Introduction --- p.72Chapter 6.2 --- Transistor Layout Techniques --- p.72Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72Chapter 6.2.2 --- Common-Centroid Structure --- p.73Chapter 6.3 --- Layout Techniques of Passive Components --- p.74Chapter 6.3.1 --- Capacitor Layout --- p.74Chapter 6.3.2 --- Resistor Layout --- p.75Chapter Chapter 7 --- Measurement Results --- p.77Chapter 7.1 --- Overview --- p.77Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80Chapter 7.3.3 --- Gain Band width Measurement --- p.81Chapter 7.3.4 --- DC Gain measurement --- p.85Chapter 7.3.5 --- Slew Rate Measurement --- p.87Chapter 7.3.6 --- Phase Margin --- p.88Chapter 7.3.7 --- Performance Summary --- p.89Chapter Chapter 8 --- Conclusions --- p.90Chapter Chapter 9 --- Appendix --- p.9

Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

Design and implementation of low power multistage amplifiers and high frequency distributed amplifiers

The advancement in integrated circuit (IC) technology has resulted in scaling down of device sizes and supply voltages without proportionally scaling down the threshold voltage of the MOS transistor. This, coupled with the increasing demand for low power, portable, battery-operated electronic devices, like mobile phones, and laptops provides the impetus for further research towards achieving higher integration on chip and low power consumption. High gain, wide bandwidth amplifiers driving large capacitive loads serve as error amplifiers in low-voltage low drop out regulators in portable devices. This demands low power, low area, and frequency-compensated multistage amplifiers capable of driving large capacitive loads. The first part of the research proposes two power and area efficient frequency compensation schemes: Single Miller Capacitor Compensation (SMC) and Single Miller Capacitor Feedforward Compensation (SMFFC), for multistage amplifiers driving large capacitive loads. The designs have been implemented in a 0.5??m CMOS process. Experimental results show that the SMC and SMFFC amplifiers achieve gain-bandwidth products of 4.6MHz and 9MHz, respectively, when driving a load of 25Kδ/120pF. Each amplifier operates from a ??1V supply, dissipates less than 0.42mW of power and occupies less than 0.02mm2 of silicon area. The inception of the latest IEEE standard like IEEE 802.16 wireless metropolitan area network (WMAN) for 10 -66 GHz range demands wide band amplifiers operating at high frequencies to serve as front-end circuits (e.g. low noise amplifier) in such receiver architectures. Devices used in cascade (multistage amplifiers) can be used to increase the gain but it is achieved at an expense of bandwidth. Distributing the capacitance associated with the input and the output of the device over a ladder structure (which is periodic), rather than considering it to be lumped can achieve an extension of bandwidth without sacrificing gain. This concept which is also known as distributed amplification has been explored in the second part of the research. This work proposes certain guidelines for the design of distributed low noise amplifiers operating at very high frequencies. Noise analysis of the distributed amplifier with real transmission lines is introduced. The analysis for gain and noise figure is verified with simulation results from a 5-stage distributed amplifier implemented in a 0.18??m CMOS process

Multipath Miller Compensation for Switched-Capacitor Systems

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator

Design of a Torque Current Generator for Strapdown Gyroscopes

The design, analysis, and experimental evaluation of an optimum performance torque current generator for use with strapdown gyroscopes, is presented. Among the criteria used to evaluate the design were the following: (1) steady-state accuracy; (2) margins of stability against self-oscillation; (3) temperature variations; (4) aging; (5) static errors drift errors, and transient errors, (6) classical frequency and time domain characteristics; and (7) the equivalent noise at the input of the comparater operational amplifier. The DC feedback loop of the torque current generator was approximated as a second-order system. Stability calculations for gain margins are discussed. Circuit diagrams are shown and block diagrams showing the implementation of the torque current generator are discussed

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature