VSS : a VHDL synthesis system

This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization. The compilation process consists of two phases. First, a design composed of generic components is synthesized from the input description. Second, this design is translated into components from a particular library by a mapper and optimized by a logic optimizer. Redesign to new technologies can be accomplished by changing only the component library

Stepwise decomposition in controlpath synthesis

A method is presented for the synthesis of the microarchitecture of controlpaths. This method is called stepwise decomposition. It focuses primarily on controlpaths of instruction set processors, however it is also applicable for more general Finite State Machine synthesis. Many of the current controlpath synthesis algorithms are based on a fixed microarchitecture, and an optimization of that microarchitecture. This stepwise decomposition method is able to synthesize microarchitectures in a range from a single PLA to multiple PLA/ROM configurations and optionally further down to hardwired, which makes it more flexible and better suited to a wider range of controlpaths than current synthesis methods. A sequence of decomposition steps, from coarse to detailed, is performed on the design to move it to the area of the design space where all constraints on space, floorplan and delay are satisfied. The method is currently implemented in APL

Mascot: Microarchitecture Synthesis of Control Paths

This paper presents MASCOT (MicroArchitecture Synthesis of ConTrol paths). This synthesis system constructs the optimal microarchitecture for a control path of an instruction set processor. Input to the system is the behavioural specification of a control path. This specification is in finite state machine form which is mapped initially onto a single programmed logic array (PLA) microarchitecture. The synthesis strategy then applies a sequence of decompositions on this initial microarchitecture. This strategy follows a decision scheme until all design objectives are met. It transforms the initial microarchitecture into a complex microarchitecture of several PLAs and ROMs. Where it is impossible to meet the design objectives, the system constructs a microarchitecture which comes as close as possible to given design objectives. Design objectives are allowed on floorplan dimensions and delay. Our strategy integrates a number of known optimization methods for specific microarchitectures. Therefore this synthesis method explores a larger part of the design space than do other control path synthesis methods. Other methods are mostly bound to one microarchitecture which they optimize. Our system is not only very flexible in microarchitecture construction but also open for extension by other optimizations

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

Estimators for Logic Minimization and Implementation Selection of Finite State machines

This paper considers two estimation problems which occur during the implementation design for a finite state machine (FSM). The first is a precise estimation of the reduction of a programmed logic array implementation (PLA) for a FSM by logic minimization. The second concerns selection of implementation alternatives based on such estimations. Estimations give the designer a quick overview of the impact of an optimization method for FSM implementation without running the actual time-consuming algorithms. The method uses curve-fitting on results found in literature for logic minimization preceded by state-assignment. Our estimations correlate by 0.97 to those results. State-graph statistics can also be used for selection of the most profitable optimization from a set of alternatives. We tested selection between a counter based implementation, partial state coding, state-assignment and topological partitioning. The goal is selection of the alternative which has the highest probability to deliver the largest minimization of the FSM. This selection method is also empirically verified by comparing its results with results obtained by running specific optimization algorithms on machines of the MCNC benchmark set

Drawing Activity Diagrams

Activity diagrams experience an increasing importance in the design and description of software systems. Unfortunately, previous approaches for automatic layout support fail or are just insufficient to capture the complexity of the related requirements. We propose a new approach tailored to the needs of activity diagrams which combines the advantages of two fundamental layout concepts called "Sugiyama's approach" and "topology-shape-metrics approach", originally developed for layered layouts of directed graphs and for orthogonal layout of undirected graphs respectively

LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

Decomposition and encoding of finite state machines for FPGA implementation

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