2,485 research outputs found

    Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

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    Area and Energy Optimizations in ASIC Implementations of AES and PRESENT Block Ciphers

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    When small, modern-day devices surface with neoteric features and promise benefits like streamlined business processes, cashierless stores, and autonomous driving, they are all too often accompanied by security risks due to a weak or absent security component. In particular, the lack of data privacy protection is a common concern that can be remedied by implementing encryption. This ensures that data remains undisclosed to unauthorized parties. While having a cryptographic module is often a goal, it is sometimes forfeited because a device's resources do not allow for the conventional cryptographic solutions. Thus, smaller, lower-energy security modules are in demand. Implementing a cipher in hardware as an application-specific integrated circuit (ASIC) will usually achieve better efficiency than alternatives like FPGAs or software, and can help towards goals such as extended battery life and smaller area footprint. The Advanced Encryption Standard (AES) is a block cipher established by the National Institute of Standards and Technology (NIST) in 2001. It has since become the most widely adopted block cipher and is applied in a variety of applications ranging from smartphones to passive RFID tags to high performance microprocessors. PRESENT, published in 2007, is a smaller lightweight block cipher designed for low-power applications. In this study, low-area and low-energy optimizations in ASICs are addressed for AES and PRESENT. In the low-area work, three existing AES encryption cores are implemented, analyzed, and benchmarked using a common fabrication technology (STM 65 nm). The analysis includes an examination of various implementations of internal AES operations and their suitability for different architectural choices. Using our taxonomy of design choices, we designed Quark-AES, a novel 8-bit AES architecture. At 1960 GE, it features a 13% improvement in area and 9% improvement in throughput/area² over the prior smallest design. To illustrate the extent of the variations due to the use of different ASIC libraries, Quark-AES and the three analyzed designs are also synthesized using three additional technologies. Even for the same transistor size, different ASIC libraries produce significantly different area results. To accommodate a variety of applications that seek different levels of tradeoffs in area and throughput, we extend all four designs to 16-bit and 32-bit datawidths. In the low-energy work, round unrolling and glitch filtering are applied together to achieve energy savings. Round unrolling, which applies multiple block cipher rounds in a combinational path, reduces the energy due to registers but increases the glitching energy. Glitch filtering complements round unrolling by reducing the amount of glitches and their associated energy consumption. For unrolled designs of PRESENT and AES, two glitch filtering schemes are assessed. One method uses AND-gates in between combinational rounds while the other used latches. Both methods work by allowing the propagation of signals only after they have stabilized. The experiments assess how energy consumption changes with respect to the degree of unrolling, the glitch filtering scheme, the degree of pipelining, the spacing between glitch filters, and the location of glitch filters when only a limited number of them can be applied due to area constraints. While in PRESENT, the optimal configuration depends on all the variables, in a larger cipher such as AES, the latch-based method consistently offers the most energy savings

    Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

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    Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

    X-ray and Near-IR Variability of the Anomalous X-ray Pulsar 1E 1048.1-5937: From Quiescence Back to Activity

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    (Abridged) We report on new and archival X-ray and near-infrared observations of the anomalous X-ray pulsar 1E 1048.1-5937 performed between 2001-2007 with RXTE, CXO, Swift, HST, and VLT. During its ~2001-2004 active period, 1E 1048.-5937 exhibited two large, long-term X-ray pulsed-flux flares as well as short bursts, and large (>10x) torque changes. Monitoring with RXTE revealed that the source entered a phase of timing stability in 2004; at the same time, a series of four simultaneous observations with CXO and HST in 2006 showed that its X-ray flux and spectrum and near-IR flux, all variable prior to 2005, stabilized. The near-IR flux, when detected by HST (H~22.7 mag) and VLT (K_S~21.0 mag), was considerably fainter than previously measured. Recently, in 2007 March, this newfound quiescence was interrupted by a sudden flux enhancement, X-ray spectral changes and a pulse morphology change, simultaneous with a large spin-up glitch and near-IR enhancement. Our RXTE observations revealed a sudden pulsed flux increase by a factor of ~3 in the 2-10 keV band. In observations with CXO and Swift, we found that the total X-ray flux increased much more than the pulsed flux, reaching a peak value of >7 times the quiescent value (2-10 keV). With these recent data, we find a strong anti-correlation between X-ray flux and pulsed fraction, and a correlation between X-ray spectral hardness and flux. Simultaneously with the radiative and timing changes, we observed a significant X-ray pulse morphology change such that the profile went from nearly sinusoidal to having multiple peaks. We compare these remarkable events with other AXP outbursts and discuss implications in the context of the magnetar model and other models of AXP emission.Comment: 13 pages (6 figures) in emulateapj style. Accepted for publication in ApJ. New version includes referee's corrections; split Figure 1 into 2 figures; modified Figs. 4b and 6b; rearranged and renumbered of some figures and sections; added an X-ray dataset; improved analysis of pulse morphology and pulsed fraction; added paragraph to sec. 3.2.

    Modeling and verifying the FlexRay physical layer protocol with reachability checking of timed automata

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    In this thesis, I report on the verification of the resilience of the FlexRay automotive bus protocol's physical layer protocol against glitches during message transmission and drifting clocks. This entailed modeling a significant part of this industrially used communictation protocol and the underlying hardware as well as the possible error scenarios in fine detail. Verifying such a complex model with model-checking led me to the development of data-structures and algorithms able to handle the associated complexity using only reasonable resources. This thesis presents such data-structures and algorithms for reachability checking of timed automata. It also present modeling principles enabling the construction of timed automata models that can be efficiently checked, as well as the models arrived at. Finally, it reports on the verified resilience of FlexRay's physical layer protocol against specific patterns of glitches under varying assumptions about the underlying hardware, like clock drift.In dieser Dissertation berichte ich über den Nachweis der Resilienz des Bitübertragungsprotokolls für die physikalische Schicht des FlexRay-Fahrzeugbusprotokolls gegenüber Übertragungsfehlern und Uhrenverschiebung. Dafür wurde es notwendig, einen signifikanten Teil dieses industriell genutzten Kommunikationsprotokolls mit seiner Hardwareumgebung und die möglichen Fehlerszenarien detailliert zu modellieren. Ein so komplexes Modell mittels Modellprüfung zu überprüfen führte mich zur Entwicklung von Datenstrukturen und Algorithmen, die die damit verbundene Komplexität mit vernünftigen Ressourcenanforderungen bewältigen können. Diese Dissertation stellt solche Datenstrukturen und Algorithmen zur Erreichbarkeitsprüfung gezeiteter Automaten vor. Sie stellt auch Modellierungsprinzipien vor, die es ermöglichen, Modelle in Form gezeiteter Automaten zu konstruieren, die effizient überprüft werden können, sowie die erstellten Modelle. Schließlich berichtet sie über die überprüfte Resilienz des FlexRay-Bitübertragungsprotokolls gegenüber spezifischen Übertragungsfehlermustern unter verschiedenen Annahmen über die Hardwareumgebung, wie etwa die Uhrenverschiebung.DFG: SFB/TRR 14 "AVACS - Automatische Verifikation und Analyse komplexer Systeme

    Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design

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    Computer hardware researchers have perennially focussed on improving the performance of computers while stipulating the energy consumption under a strict budget. While several innovations over the years have led to high performance and energy efficient computers, more challenges have also emerged as a fallout. For example, smaller transistor devices in modern multi-core systems are afflicted with several reliability and security concerns, which were inconceivable even a decade ago. Tackling these bottlenecks happens to negatively impact the power and performance of the computers. This dissertation explores novel techniques to gracefully solve some of the pressing challenges of the modern computer design. Specifically, the proposed techniques improve the reliability of on-chip communication fabric under a high power supply noise, increase the energy-efficiency of low-power graphics processing units, and demonstrate an unprecedented security loophole of the low-power computing paradigm through rigorous hardware-based experiments

    Low-power digital processor for wireless sensor networks

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    Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 69-72).In order to make sensor networks cost-effective and practical, the electronic components of a wireless sensor node need to run for months to years on the same battery. This thesis explores the design of a low-power digital processor for these sensor nodes, employing techniques such as hardwired algorithms, lowered supply voltages, clock gating and subsystem shutdown. Prototypes were built on both a FPGA and ASIC platform, in order to verify functionality and characterize power consumption. The resulting 0.18[micro]m silicon fabricated in National Semiconductor Corporation's process was operational for supply voltages ranging from 0.5V to 1.8V. At the lowest operating voltage of 0.5V and a frequency of 100KHz, the chip performs 8 full-accuracy FFT computations per second and draws 1.2nJ of total energy per cycle. Although this energy/cycle metric does not surpass existing low-energy processors demonstrated in literature or commercial products, several low-power techniques are suggested that could drastically improve the energy metrics of a future implementation.by Daniel Frederic Finchelstein.S.M

    Study Of The Relationship Between Delta Delay And Adjacent Parallel Wire Length In 45 Nanometer Process Technology

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    Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL), synthesis, place and route, timing closure and various other analyses before sign-off. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key issue for Deep Sub-Micron design. Post silicon bug due to noise and signal integrity can be prevented and fixed at early stage of the IC design cycle. The purpose of this research is to establish a preventive measurement for adjacent wire that can travel in parallel for 45nm technology. The intention is to ensure that a complex design can be delivered to the market with accurate, fast and trusted analysis and provide sign-off solution. Main approach is to conduct the relationship study between delta delay and adjacent parallel wire in 45 nanometer (nm) process technology and provide a preventive measurement to limit the adjacent wire can travel in parallel. The design is explored thoroughly to study the relationship between delay noise and adjacent parallel wire. The correlation is translated into an equation to estimate the delay noise produced with a certain length of adjacent parallel wire
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