Optimising bandwidth over deep sub-micron interconnect.

In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When relatively long wires are placed in parallel, it is essential to include the effects of cross-talk on delay. In a parallel wire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Repeater insertion depending on whether it is optimal or constrained, affects the delay in different ways. Considering all these effects we show that there is a clear optimum configuration for the wires which maximises the total bandwidth. Our analysis is valid for lossy interconnects as are typical of wires in DSM technologies

The influence of surface currents on pattern-dependent charging and notching

Surface charge dissipation on insulator surfaces can reduce local charging potentials thereby preventing ion trajectory deflection at the bottom of trenches that leads to lateral sidewall etching (notching). We perform detailed Monte Carlo simulations of pattern-dependent charging during etching in high-density plasmas with the maximum sustainable surface electric field as a parameter. Significant notching occurs for a threshold electric field as low as 0.5 MV/cm or 50 V/µm, which is reasonable for the surface of good insulators. The results support pattern-dependent charging as the leading cause of notching and suggest that the problem will disappear as trench widths are reduced