Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation. We first describe a deterministic broadside test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same test. To reduce the complexity of test generation, sub-procedures with low complexity are applied before a complete branch-and-bound procedure. Next, we describe a method based on static timing analysis to select critical paths for test generation. Logic conditions that are necessary for detecting a path delay fault are considered to refine the accuracy of static timing analysis, using input necessary assignments. Input necessary assignments are input values that must be assigned to detect a fault. The method calculates more accurate path delays, selects paths that are critical during test application, and identifies undetectable path delay faults. These two methods are applicable to off-line test generation. For large circuits with high complexity and frequency, built-in test generation is a cost-effective method for delay testing. For a circuit that is embedded in a larger design, we developed a method for built-in generation of functional broadside tests to avoid excessive power dissipation during test application and the overtesting of delay faults, taking the functional constraints on the primary input sequences of the circuit into consideration. Functional broadside tests are scan-based two-pattern tests for delay faults that create functional operation conditions during test application. To avoid the potential fault coverage loss due to the exclusive use of functional broadside tests, we also developed an optional DFT method based on state holding to improve fault coverage. High delay fault coverage can be achieved by the developed method for benchmark circuits using simple hardware

Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations

The current design and manufacturing semiconductor technologies require to test the products against delay related defects. However, complex acpSOC require low-overhead testability methods to keep the test cost at an acceptable level. Skewed-load tests seem to be the appropriate way to test delay faults in these acpSOC because the test application requires only one storage element per scan cell. Compressed skewed-load test generator based on genetic algorithm is proposed for wrapper-based logic cores of acpSOC. Deterministic population initialization is used to ensure the highest achievable aclTDF coverage for the given wrapper and scan cell order. The developed method performs test data compression by generating test vectors containing already overlapped test vector pairs. The experimental results show high fault coverages, decreased test lengths and better scalability in comparison to recent methods

Power supply noise in delay testing

As technology scales into the Deep Sub-Micron (DSM) regime, circuit designs have become more and more sensitive to power supply noise. Excessive noise can significantly affect the timing performance of DSM designs and cause non-trivial additional delay. In delay test generation, test compaction and test fill techniques can produce excessive power supply noise. This will eventually result in delay test overkill. To reduce this overkill, we propose a low-cost pattern-dependent approach to analyze noise-induced delay variation for each delay test pattern applied to the design. Two noise models have been proposed to address array bond and wire bond power supply networks, and they are experimentally validated and compared. Delay model is then applied to calculate path delay under noise. This analysis approach can be integrated into static test compaction or test fill tools to control supply noise level of delay tests. We also propose an algorithm to predict transition count of a circuit, which can be applied to control switching activity during dynamic compaction. Experiments have been performed on ISCAS89 benchmark circuits. Results show that compacted delay test patterns generated by our compaction tool can meet a moderate noise or delay constraint with only a small increase in compacted test set size. Take the benchmark circuit s38417 for example: a 10% delay increase constraint only results in 1.6% increase in compacted test set size in our experiments. In addition, different test fill techniques have a significant impact on path delay. In our work, a test fill tool with supply noise analysis has been developed to compare several test fill techniques, and results show that the test fill strategy significant affect switching activity, power supply noise and delay. For instance, patterns with minimum transition fill produce less noise-induced delay than random fill. Silicon results also show that test patterns filled in different ways can cause as much as 14% delay variation on target paths. In conclusion, we must take noise into consideration when delay test patterns are generated

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra

Scan-based delay test achieves high fault coverage due to its improved controllability and observability. This is particularly important for our K Longest Paths Per Gate (KLPG) test approach, which has additional necessary assignments on the paths. At the same time, some percentage of the flip-flops in the circuit will not scan, increasing the difficulty in test generation. In particular, there is no direct control on the outputs of those non-scan cells. All the non-scan cells that cannot be initialized are considered “uncontrollable” in the test generation process. They behave like “black boxes” and, thus, may block a potential path propagation, resulting in path delay test coverage loss. It is common for the timing critical paths in a circuit to pass through nodes influenced by the non-scan cells. In our work, we have extended the traditional Boolean algebra by including the “uncontrolled” state as a legal logic state, so that we can improve path coverage. Many path pruning decisions can be taken much earlier and many of the lost paths due to uncontrollable non-scan cells can be recovered, increasing path coverage and potentially reducing average CPU time per path. We have extended the existing traditional algebra to an 11-value algebra: Zero (stable), One (stable), Unknown, Uncontrollable, Rise, Fall, Zero/Uncontrollable, One/Uncontrollable, Unknown/Uncontrollable, Rise/Uncontrollable, and Fall/Uncontrollable. The logic descriptions for the NOT, AND, NAND, OR, NOR, XOR, XNOR, PI, Buff, Mux, TSL, TSH, TSLI, TSHI, TIE1 and TIE0 cells in the ISCAS89 benchmark circuits have been extended to the 11-value truth table. With 10% non-scan flip-flops, improved path delay fault coverage has been observed in comparison to that with the traditional algebra. The greater the number of long paths we want to test; the greater the path recovery advantage we achieve using our algebra. Along with improved path recovery, we have been able to test a greater number of transition fault sites. In most cases, the average CPU time per path is also lower while using the 11-value algebra. The number of tested paths increased by an average of 1.9x for robust tests, and 2.2x for non-robust tests, for K=5 (five longest rising and five longest falling transition paths through each line in the circuit), using the eleven-value algebra in contrast to the traditional algebra. The transition fault coverage increased by an average of 70%. The improvement increased with higher K values. The CPU time using the extended algebra increased by an average of 20%. So the CPU time per path decreased by an average of 40%. In future work, the extended algebra can achieve better test coverage for memory intensive circuits, circuits with logic black boxes, third party IPs, and analog units

Technology 2001: The Second National Technology Transfer Conference and Exposition, volume 1

Papers from the technical sessions of the Technology 2001 Conference and Exposition are presented. The technical sessions featured discussions of advanced manufacturing, artificial intelligence, biotechnology, computer graphics and simulation, communications, data and information management, electronics, electro-optics, environmental technology, life sciences, materials science, medical advances, robotics, software engineering, and test and measurement

The sedimentary and geomorphic signature of subglacial processes in the Tarfala Valley, northern Sweden, and the links between subglacial soft-bed deformation, glacier flow dynamics, and landform generation

The aim of this study is to understand the extent, depth, magnitude and significance of subglacial sediment deformation. It will examine the role of this deformation in controlling glacier dynamics and landform generation in glaciers in general, and polythermal glaciers in particular. A detailed multi-dimensional approach is used to study recently exposed glacigenic sediments on the forefields of three polyglaciers in the Tarfala Valley, northern Sweden. Overridden fluted moraines and diamicton plains occur in each forefield. These palimpsest landforms consist of multiple subglacial traction tills. Flutes have quasi-regular geometry and about half of those studied have no initiating boulder. It is suggested here that flute formation by forced-mechanisms was superimposed on flute formation related to a topographically-induced flow instability. In each forefield the depth of the deforming-bed averaged between 0.2m and 0.6m thickness. Detailed clast fabric data suggest the diamicton plain is composed of thin layers of traction tills that accreted over time as the zone of deformation moved upwards. Laboratory shear box tests show that subglacial deformation required elevated pore-water pressures, which suggests deforming-bed conditions and flute formation were restricted to the temperate zones of polythermal glaciers. Magnetic fabrics suggest strain magnitudes were moderate (≤10), rather than the very high strain magnitudes (>102) required by the deforming-bed model. The application of the micro-structural mapping technique demonstrates that subglacial deformation was multi-phase, heterogeneous, and partitioned into the softer and more easily deformed parts of the matrix. Consequently, deformation is controlled by variations in sediment granulometry and pore-water pressure, and is likely to have been spatially and temporally variable, a finding that supports the ice-bed mosaic model. The strain magnitudes and deforming-bed thickness suggest that soft-bed deformation did not exert a major control on glacier dynamics during the Little Ice Age advance

Abstracts on Radio Direction Finding (1899 - 1995)

The files on this record represent the various databases that originally composed the CD-ROM issue of "Abstracts on Radio Direction Finding" database, which is now part of the Dudley Knox Library's Abstracts and Selected Full Text Documents on Radio Direction Finding (1899 - 1995) Collection. (See Calhoun record https://calhoun.nps.edu/handle/10945/57364 for further information on this collection and the bibliography). Due to issues of technological obsolescence preventing current and future audiences from accessing the bibliography, DKL exported and converted into the three files on this record the various databases contained in the CD-ROM. The contents of these files are: 1) RDFA_CompleteBibliography_xls.zip [RDFA_CompleteBibliography.xls: Metadata for the complete bibliography, in Excel 97-2003 Workbook format; RDFA_Glossary.xls: Glossary of terms, in Excel 97-2003 Workbookformat; RDFA_Biographies.xls: Biographies of leading figures, in Excel 97-2003 Workbook format]; 2) RDFA_CompleteBibliography_csv.zip [RDFA_CompleteBibliography.TXT: Metadata for the complete bibliography, in CSV format; RDFA_Glossary.TXT: Glossary of terms, in CSV format; RDFA_Biographies.TXT: Biographies of leading figures, in CSV format]; 3) RDFA_CompleteBibliography.pdf: A human readable display of the bibliographic data, as a means of double-checking any possible deviations due to conversion

Molecular phylogeny of horseshoe crab using mitochondrial Cox1 gene as a benchmark sequence

An effort to assess the utility of 650 bp Cytochrome C oxidase subunit I (DNA barcode) gene in delineating the members horseshoe crabs (Family: xiphosura) with closely related sister taxa was made. A total of 33 sequences were extracted from National Center for Biotechnological Information (NCBI) which include horseshoe crabs, beetles, common crabs and scorpion sequences. Constructed phylogram showed beetles are closely related with horseshoe crabs than common crabs. Scorpion spp were distantly related to xiphosurans. Phylogram and observed genetic distance (GD) date were also revealed that Limulus polyphemus was closely related with Tachypleus tridentatus than with T.gigas. Carcinoscorpius rotundicauda was distantly related with L.polyphemus. The observed mean Genetic Distance (GD) value was higher in 3rd codon position in all the selected group of organisms. Among the horseshoe crabs high GC content was observed in L.polyphemus (38.32%) and lowest was observed in T.tridentatus (32.35%). We conclude that COI sequencing (barcoding) could be used in identifying and delineating evolutionary relatedness with closely related specie

Crab and cockle shells as heterogeneous catalysts in the production of biodiesel

In the present study, the waste crab and cockle shells were utilized as source of calcium oxide to transesterify palm olein into methyl esters (biodiesel). Characterization results revealed that the main component of the shells are calcium carbonate which transformed into calcium oxide upon activated above 700 °C for 2 h. Parametric studies have been investigated and optimal conditions were found to be catalyst amount, 5 wt.% and methanol/oil mass ratio, 0.5:1. The waste catalysts perform equally well as laboratory CaO, thus creating another low-cost catalyst source for producing biodiesel. Reusability results confirmed that the prepared catalyst is able to be reemployed up to five times. Statistical analysis has been performed using a Central Composite Design to evaluate the contribution and performance of the parameters on biodiesel purity