System-Level Access to On-Chip Instruments

Modern integrated circuits (ICs) contain thousands of instruments to enable testing, tuning, monitoring, and so on. These on-chip instruments must be accessed through the ICs’ life- time. However, when ICs are mounted on Printed Circuit Boards (PCBs), access from system-level is challenged due to complex system hierarchies with a multitude of interfaces. In this paper we enable access from system-level to chip-level instruments by proposing hardware, protocol, and communication schemes. We have validated our scheme by implementing a system with two ICs on a Field-Programmable Gate Array (FPGA) where each IC includes an IEEE Std. 1687 network, communication between ICs is with Serial Peripheral Interface (SPI) and communication with the outside is with Universal Asynchronous Receiver Transmitter (UART). In experiments we evaluate communication based on software (polling) and hardware (interrupt) as well as overhead in terms of transported data and needed area

Accessing general IEEE Std. 1687 networks via functional ports

Reconfigurable scan networks (RSNs), like IEEE Std. 1687 networks, offer flexible and scalable access to embedded (on- chip) instruments. These networks are typically accessed from the outside via a dedicated test port, like the test access port (TAP) of IEEE Std. 1149.1. As not all integrated circuits have a dedicated test port, the IEEE Std. P1687.1 working group is exploring how existing functional ports can be used. Fundamental challenges are to determine what hardware to include in the component translating information between a functional port and an IEEE Std. 1687 network and to describe a protocol for the data transported over a functional interface. We have previously shown hardware and protocol to access a limited type of IEEE Std. 1687 networks, known as flat segment insertion bit (SIB)-based networks. In this paper, we present a solution to handle general IEEE Std. 1687 networks. We have made a number of implementations with various benchmarks on an FPGA to evaluate the data overhead and the area usage

Modelling and characterization of Quantum Dots as QLED devices for automotive lighting systems

This work reports the design, manufacturing and numerical simulation approach of an electroluminescent quantum dot light emitting device (QLED) based on quantum dots as an active layer. In addition, the electrical I-V curve was measured, observing how the fabrication process and layer thickness have an influence in the shape of the plot. This experimental device enabled us to create a computational model for the QLED based on the Transfer Hamiltonian approach to calculate the current density J(mA/cm2), the band diagram of the system and the accumulated charge distribution. Thanks to the QLED simulator developed, it would be possible to model the device and anticipate the electrical performance in a theoretical design step before going to QLED manufacturing at the laboratory. Eventually, particular automotive lighting system demonstrators were designed to integrate the theoretical and experimental research carried out in an industrial automotive product.Tesis Univ. Granada

FlexClock: Generic Clock Reconfiguration for Low-end IoT Devices

Clock configuration within constrained general-purpose microcontrollers takes a key role in tuning performance, power consumption, and timing accuracy of applications in the Internet of Things (IoT). Subsystems governing the underlying clock tree must nonetheless cope with a huge parameter space, complex dependencies, and dynamic constraints. Manufacturers expose the underlying functions in very diverse ways, which leads to specialized implementations of low portability. In this paper, we propose FlexClock, an approach for generic online clock reconfiguration on constrained IoT devices. We argue that (costly) generic clock configuration of general purpose computers and powerful mobile devices need to slim down to the lower end of the device spectrum. In search of a generalized solution, we identify recurring patterns and building blocks, which we use to decompose clock trees into independent, reusable components. With this segmentation we derive an abstract representation of vendor-specific clock trees, which then can be dynamically reconfigured at runtime. We evaluate our implementation on common hardware. Our measurements demonstrate how FlexClock significantly improves peak power consumption and energy efficiency by enabling dynamic voltage and frequency scaling (DVFS) in a platform-agnostic way

Model for Predicting Bluetooth Low Energy Micro-Location Beacon Coin Cell Battery Lifetime

Bluetooth Low Energy beacon devices, typically operating on coin cell batteries, have emerged as key components of micro-location wireless sensor networks. To design efficient and reliable networks, designers require tools for predicting battery and beacon lifetime, based on design parameters that are specific to micro-location applications. This design science research contributes to the implementation of an artifact functioning as a predictive tool for coin cell battery lifetime when powering Bluetooth Low Energy beacon devices. Building upon effective and corroborated components from other researchers, the Beacon Lifetime Model 1.0 was developed as a spreadsheet workbook, providing a user interface for designers to specify parameters, and providing a predictive engine to predict coin cell battery lifetime. Results showed that the measured and calculated predictions were consistent with those derived through other methodologies, while providing a uniquely extensible user interface which may accommodate future work on emerging components. Future work may include research on real world scenarios, as beacon devices are deployed for robust micro-location applications. Future work may also include improved battery models that capture increasingly accurate performance under micro-location workloads. Beacon Lifetime Model 1.x is designed to incorporate those emerging components, with Beacon Lifetime Model1.0 serving as the initial instantiation of this design science artifact

Experimental evidence of ground albedo neutron impact on Soft Error Rate for nanoscale devices

International audienceThis work demonstrates the experimental evidence of ground albedo neutron impact on Soft Error Rate (SER) for nanoscale devices. The SER of a 45 nm technology was measured according to an experimental protocol using a californium sealed source and several scenes based on material blocks. High density polyethylene and concrete materials were considered to investigate the intrinsic role in albedo neutron productions and their effect on devices. Results show the impact in the spectrum concern mainly energies below 5 MeV. Devices are characterized by a sensitivity which varies according to the presence or not of thethe material block. Simulations using GEANT4 and MUSCA SEP3 tool were performed to extend analyses. A final part is devoted to investigate the impact of ground albedo neutrons on SER by considering realistic terrestrial neutron field

Lower-order compensation chain threshold-reduction technique for multi-stage voltage multipliers

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal

Evolvable Smartphone-Based Point-of-Care Systems For In-Vitro Diagnostics

Recent developments in the life-science -omics disciplines, together with advances in micro and nanoscale technologies offer unprecedented opportunities to tackle some of the major healthcare challenges of our time. Lab-on-Chip technologies coupled with smart-devices in particular, constitute key enablers for the decentralization of many in-vitro medical diagnostics applications to the point-of-care, supporting the advent of a preventive and personalized medicine. Although the technical feasibility and the potential of Lab-on-Chip/smart-device systems is repeatedly demonstrated, direct-to-consumer applications remain scarce. This thesis addresses this limitation. System evolvability is a key enabler to the adoption and long-lasting success of next generation point-of-care systems by favoring the integration of new technologies, streamlining the reengineering efforts for system upgrades and limiting the risk of premature system obsolescence. Among possible implementation strategies, platform-based design stands as a particularly suitable entry point. One necessary condition, is for change-absorbing and change-enabling mechanisms to be incorporated in the platform architecture at initial design-time. Important considerations arise as to where in Lab-on-Chip/smart-device platforms can these mechanisms be integrated, and how to implement them. Our investigation revolves around the silicon-nanowire biological field effect transistor, a promising biosensing technology for the detection of biological analytes at ultra low concentrations. We discuss extensively the sensitivity and instrumentation requirements set by the technology before we present the design and implementation of an evolvable smartphone-based platform capable of interfacing lab-on-chips embedding such sensors. We elaborate on the implementation of various architectural patterns throughout the platform and present how these facilitated the evolution of the system towards one accommodating for electrochemical sensing. Model-based development was undertaken throughout the engineering process. A formal SysML system model fed our evolvability assessment process. We introduce, in particular, a model-based methodology enabling the evaluation of modular scalability: the ability of a system to scale the current value of one of its specification by successively reengineering targeted system modules. The research work presented in this thesis provides a roadmap for the development of evolvable point-of-care systems, including those targeting direct-to-consumer applications. It extends from the early identification of anticipated change, to the assessment of the ability of a system to accommodate for these changes. Our research should thus interest industrials eager not only to disrupt, but also to last in a shifting socio-technical paradigm