Antimonotonicity, Crisis and Multiple Attractors in a Simple Memristive Circuit

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Colpitts Chaotic Oscillator Coupling with a Generalized Memristor

By introducing a generalized memristor into a fourth-order Colpitts chaotic oscillator, a new memristive Colpitts chaotic oscillator is proposed in this paper. The generalized memristor is equivalent to a diode bridge cascaded with a first-order parallel RC filter. Chaotic attractors of the oscillator are numerically revealed from the mathematical model and experimentally captured from the physical circuit. The dynamics of the memristive Colpitts chaotic oscillator is investigated both theoretically and numerically, from which it can be found that the oscillator has a unique equilibrium point and displays complex nonlinear phenomena

Synthesis of memristive one-port circuits with piecewise-smooth characteristics

A generalized approach for the implementation of memristive two-terminal circuits with piesewise-smooth characteristics is proposed on the example of a multifunctional circuit based on a transistor switch. Two versions of the circuit are taken into consideration: an experimental model of the piecewise-smooth memristor (Chua's memristor) and a piecewise-smooth memristive capacitor. Physical experiments are combined with numerical modelling of the discussed circuit models. Thus, it is demonstrated that the considered circuit is a flexible solution for synthesis of a wide range of memristive systems with tuneable characteristics.Comment: 3 pages, 3 figure

Memristor Platforms for Pattern Recognition Memristor Theory, Systems and Applications

In the last decade a large scientific community has focused on the study of the memristor. The memristor is thought to be by many the best alternative to CMOS technology, which is gradually showing its flaws. Transistor technology has developed fast both under a research and an industrial point of view, reducing the size of its elements to the nano-scale. It has been possible to generate more and more complex machinery and to communicate with that same machinery thanks to the development of programming languages based on combinations of boolean operands. Alas as shown by Moore’s law, the steep curve of implementation and of development of CMOS is gradually reaching a plateau. It is clear the need of studying new elements that can combine the efficiency of transistors and at the same time increase the complexity of the operations. Memristors can be described as non-linear resistors capable of maintaining memory of the resistance state that they reached. From their first theoretical treatment by Professor Leon O. Chua in 1971, different research groups have devoted their expertise in studying the both the fabrication and the implementation of this new promising technology. In the following thesis a complete study on memristors and memristive elements is presented. The road map that characterizes this study departs from a deep understanding of the physics that govern memristors, focusing on the HP model by Dr. Stanley Williams. Other devices such as phase change memories (PCMs) and memristive biosensors made with Si nano-wires have been studied, developing emulators and equivalent circuitry, in order to describe their complex dynamics. This part sets the first milestone of a pathway that passes trough more complex implementations such as neuromorphic systems and neural networks based on memristors proving their computing efficiency. Finally it will be presented a memristror-based technology, covered by patent, demonstrating its efficacy for clinical applications. The presented system has been designed for detecting and assessing automatically chronic wounds, a syndrome that affects roughly 2% of the world population, through a Cellular Automaton which analyzes and processes digital images of ulcers. Thanks to its precision in measuring the lesions the proposed solution promises not only to increase healing rates, but also to prevent the worsening of the wounds that usually lead to amputation and death

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing

Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves the path towards a promising solution to future energy-efficient real-time computing systems. However, existing silicon neuron approaches are designed to faithfully reproduce biological neuron dynamics, and hence they are incompatible with the RRAM synapses, or require extensive peripheral circuitry to modulate a synapse, and are thus deficient in learning capability. As a result, they eliminate most of the density advantages gained by the adoption of nanoscale devices, and fail to realize a functional computing system. This dissertation describes novel hardware architectures and neuron circuit designs that synergistically assemble the fundamental and significant elements for brain-inspired computing. Versatile CMOS spiking neurons that combine integrate-and-fire, passive dense RRAM synapses drive capability, dynamic biasing for adaptive power consumption, in situ spike-timing dependent plasticity (STDP) and competitive learning in compact integrated circuit modules are presented. Real-world pattern learning and recognition tasks using the proposed architecture were demonstrated with circuit-level simulations. A test chip was implemented and fabricated to verify the proposed CMOS neuron and hardware architecture, and the subsequent chip measurement results successfully proved the idea. The work described in this dissertation realizes a key building block for large-scale integration of spiking neural network hardware, and then, serves as a step-stone for the building of next-generation energy-efficient brain-inspired cognitive computing systems