New virtually scaling free adaptive CORDIC rotator

In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2

A 16-bit CORDIC rotator for high-performance wireless LAN

In this paper we propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm2 and it dissipates 7 mW power at 20 MHz frequency

Computational structures for robotic computations

The computational problem of inverse kinematics and inverse dynamics of robot manipulators by taking advantage of parallelism and pipelining architectures is discussed. For the computation of inverse kinematic position solution, a maximum pipelined CORDIC architecture has been designed based on a functional decomposition of the closed-form joint equations. For the inverse dynamics computation, an efficient p-fold parallel algorithm to overcome the recurrence problem of the Newton-Euler equations of motion to achieve the time lower bound of O(log sub 2 n) has also been developed

CORDIC algorithm and its applications

openThe CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation.The CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation

A Joint Filter and Spectrum Shifting Architecture for Low Complexity Flexible UFMC in 5G

© 2021 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.[EN] The hardware realization of Universal Filtered Multi Carrier (UFMC) architecture has attracted significant attention in fifth generation (5G) and beyond. In addition to the flexibility in fast Fourier transform (FFT)-length, a flexible prototype filter in combination with multiplicative complex spectrum shifting co-efficients is required for realizing flexible UFMC architecture. The existing architectures of UFMC transmitter commonly adopted fixed-size FFT-length, number of subbands, subband size, and filter-length. Moreover, the lack of flexible prototype filter and spectrum localization of filter co-efficients to individual subbands limits the flexible UFMC system design. In this paper, we propose VLSI architecture for a flexible length prototype filter that can generate spectrally shifted filter co-efficients to individual subbands in tune with the changing value of FFT-length, number of subbands, subband size, and filter-length. For 16-bit word size architecture, our proposed design produces filter co-efficients and spectrum shifting co-efficients upto length, 2(15). Thus, any desired combination of FFT-length, number of subbands, subband size and filter-length is selected to generate the filter co-efficients for the individual subbands. Moreover, complex multiplication and addition operations are reduced in proposed architecture, quantitatively, about 58.81% reduction in filtering unit is achieved over the state-of-the-art architecture. Finally, hardware implementation output and XILINX post route simulation result matches perfectly with MATLAB simulations.Kumar, V.; Mukherjee, M.; Lloret, J.; Ren, Z.; Kumari, M. (2021). A Joint Filter and Spectrum Shifting Architecture for Low Complexity Flexible UFMC in 5G. IEEE Transactions on Wireless Communications. 20(10):6706-6714. https://doi.org/10.1109/TWC.2021.3076039S67066714201

Phase Estimation for Grid Synchronization of DG System Using Cordic Algorithm

The proper operation of grid connected inverter system is determined by grid voltage conditions such as phase, amplitude and frequency. In such applications, an accurate and fast detection of the phase angle, amplitude and frequency of the grid voltage is essential for reference current generation. Phase angle plays an important role in control being used to transform the feedback variables to a suitable reference frame in which the control structure is implemented. Hence grid synchronization has a significant role in the control of grid connected inverter system. However, accurate on-line tracking of phase angle of the grid voltages under distorted grid condition is critical especially; during line notching, voltage unbalance, voltage dips, frequency variations etc. This project work involves development of phase estimation technique for grid synchronization using CORDIC algorithm during unbalanced three-phase grid voltage conditions. By proposing CORDIC algorithm, we can largely reduce the computational time while it will be implemented in real time platform using FPGA or DSP. Computer simulations have been carried out using MATLAB-Simulink package for feasibility of the study

Mimo Systems Low complexity SVD Implementation Analysis

This paper analyses the implementation of the singular value decomposition (SVD) using approximation to the exact computation for MIMO systems in the case of modulation-mode and power assignment set-up. The study developed in the paper focuses on the use of low complexity algorithm with low computational load oriented to the use of devices with limited resources as FPGA, highlighting some of the advantages and drawbacks against more sophisticated devices. The implementation of the SVD is analyzed through the algorithms that efficiently perform the required computations, seeking for computationally efficient solutions that provide parallelism and low complexity. The CORDIC algorithm seems to be a good candidate for this task since it can efficiently compute the singular value decomposition. It is shown that this algorithm provides an efficient tool for SVD computation with appropriate accuracy and the computational complexity obtained and the required resources make it feasible to be implemented on an FPGA device. System performance degradation is analyzed compared with conventional and exact method for SVD obtaining some key conclusions