Testing for delay defects utilizing test data compression techniques

textAs technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X’s) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X’s. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.Electrical and Computer Engineerin

Time series prediction and channel equalizer using artificial neural networks with VLSI implementation

The architecture and training procedure of a novel recurrent neural network (RNN), referred to as the multifeedbacklayer neural network (MFLNN), is described in this paper. The main difference of the proposed network compared to the available RNNs is that the temporal relations are provided by means of neurons arranged in three feedback layers, not by simple feedback elements, in order to enrich the representation capabilities of the recurrent networks. The feedback layers provide local and global recurrences via nonlinear processing elements. In these feedback layers, weighted sums of the delayed outputs of the hidden and of the output layers are passed through certain activation functions and applied to the feedforward neurons via adjustable weights. Both online and offline training procedures based on the backpropagation through time (BPTT) algorithm are developed. The adjoint model of the MFLNN is built to compute the derivatives with respect to the MFLNN weights which are then used in the training procedures. The Levenberg–Marquardt (LM) method with a trust region approach is used to update the MFLNN weights. The performance of the MFLNN is demonstrated by applying to several illustrative temporal problems including chaotic time series prediction and nonlinear dynamic system identification, and it performed better than several networks available in the literature

Automated Design Space Exploration and Datapath Synthesis for Finite Field Arithmetic with Applications to Lightweight Cryptography

Today, emerging technologies are reaching astronomical proportions. For example, the Internet of Things has numerous applications and consists of countless different devices using different technologies with different capabilities. But the one invariant is their connectivity. Consequently, secure communications, and cryptographic hardware as a means of providing them, are faced with new challenges. Cryptographic algorithms intended for hardware implementations must be designed with a good trade-off between implementation efficiency and sufficient cryptographic strength. Finite fields are widely used in cryptography. Examples of algorithm design choices related to finite field arithmetic are the field size, which arithmetic operations to use, how to represent the field elements, etc. As there are many parameters to be considered and analyzed, an automation framework is needed. This thesis proposes a framework for automated design, implementation and verification of finite field arithmetic hardware. The underlying motif throughout this work is “math meets hardware”. The automation framework is designed to bring the awareness of underlying mathematical structures to the hardware design flow. It is implemented in GAP, an open source computer algebra system that can work with finite fields and has symbolic computation capabilities. The framework is roughly divided into two phases, the architectural decisions and the automated design genera- tion. The architectural decisions phase supports parameter search and produces a list of candidates. The automated design generation phase is invoked for each candidate, and the generated VHDL files are passed on to conventional synthesis tools. The candidates and their implementation results form the design space, and the framework allows rapid design space exploration in a systematic way. In this thesis, design space exploration is focused on finite field arithmetic. Three distinctive features of the proposed framework are the structure of finite fields, tower field support, and on the fly submodule generation. Each finite field used in the design is represented as both a field and its corresponding vector space. It is easy for a designer to switch between fields and vector spaces, but strict distinction of the two is necessary for hierarchical designs. When an expression is defined over an extension field, the top-level module contains element signals and submodules for arithmetic operations on those signals. The submodules are generated with corresponding vector signals and the arithmetic operations are now performed on the coordinates. For tower fields, the submodules are generated for the subfield operations, and the design is generated in a top-down fashion. The binding of expressions to the appropriate finite fields or vector spaces and a set of customized methods allow the on the fly generation of expressions for implementation of arithmetic operations, and hence submodule generation. In the light of NIST Lightweight Cryptography Project (LWC), this work focuses mainly on small finite fields. The thesis illustrates the impact of hardware implementation results during the design process of WAGE, a Round 2 candidate in the NIST LWC standardization competition. WAGE is a hardware oriented authenticated encryption scheme. The parameter selection for WAGE was aimed at balancing the security and hardware implementation area, using hardware implementation results for many design decisions, for example field size, representation of field elements, etc. In the proposed framework, the components of WAGE are used as an example to illustrate different automation flows and demonstrate the design space exploration on a real-world algorithm

ERROR IDENTIFICATION IN RAM USING INPUT VECTOR MONITORING CONCURRENT BIST ARCHITECTURE

Abstract— Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the Random Access Memory without imposing a need to set the RAM offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff.

Efficient local search for Pseudo Boolean Optimization

Algorithms and the Foundations of Software technolog

Efficient complementary sequences-based architectures and their application to ranging measurements

Premio Extraordinario de Doctorado de la UAH en 2015En las últimas décadas, los sistemas de medición de distancias se han beneficiado de los avances en el área de las comunicaciones inalámbricas. En los sistemas basados en CDMA (Code-Division Multiple-Access), las propiedades de correlación de las secuencias empleadas juegan un papel fundamental en el desarrollo de dispositivos de medición de altas prestaciones. Debido a las sumas ideales de correlaciones aperiódicas, los conjuntos de secuencias complementarias, CSS (Complementary Sets of Sequences), son ampliamente utilizados en sistemas CDMA. En ellos, es deseable el uso de arquitecturas eficientes que permitan generar y correlar CSS del mayor número de secuencias y longitudes posibles. Por el término eficiente se hace referencia a aquellas arquitecturas que requieren menos operaciones por muestra de entrada que con una arquitectura directa. Esta tesis contribuye al desarrollo de arquitecturas eficientes de generación/correlación de CSS y derivadas, como son las secuencias LS (Loosely Synchronized) y GPC (Generalized Pairwise Complementary), que permitan aumentar el número de longitudes y/o de secuencias disponibles. Las contribuciones de la tesis pueden dividirse en dos bloques: En primer lugar, las arquitecturas eficientes de generación/correlación para CSS binarios, derivadas en trabajos previos, son generalizadas al alfabeto multinivel (secuencias con valores reales) mediante el uso de matrices de Hadamard multinivel. Este planteamiento tiene dos ventajas: por un lado el aumento del número de longitudes que pueden generarse/correlarse y la eliminación de las limitaciones de las arquitecturas previas en el número de secuencias en el conjunto. Por otro lado, bajo ciertas condiciones, los parámetros de las arquitecturas generalizadas pueden ajustarse para generar/correlar eficientemente CSS binarios de mayor número de longitudes que con las arquitecturas eficientes previas. En segundo lugar, las arquitecturas propuestas son usadas para el desarrollo de nuevos algoritmos de generación/correlación de secuencias derivadas de CSS que reducen el número de operaciones por muestra de entrada. Finalmente, se presenta la aplicación de las secuencias estudiadas en un nuevo sistema de posicionamiento local basado en Ultra-Wideband y en un sistema de posicionamiento local basado en ultrasonidos

Applications of MATLAB in Science and Engineering

The book consists of 24 chapters illustrating a wide range of areas where MATLAB tools are applied. These areas include mathematics, physics, chemistry and chemical engineering, mechanical engineering, biological (molecular biology) and medical sciences, communication and control systems, digital signal, image and video processing, system modeling and simulation. Many interesting problems have been included throughout the book, and its contents will be beneficial for students and professionals in wide areas of interest

Pattern Recognition

Pattern recognition is a very wide research field. It involves factors as diverse as sensors, feature extraction, pattern classification, decision fusion, applications and others. The signals processed are commonly one, two or three dimensional, the processing is done in real- time or takes hours and days, some systems look for one narrow object class, others search huge databases for entries with at least a small amount of similarity. No single person can claim expertise across the whole field, which develops rapidly, updates its paradigms and comprehends several philosophical approaches. This book reflects this diversity by presenting a selection of recent developments within the area of pattern recognition and related fields. It covers theoretical advances in classification and feature extraction as well as application-oriented works. Authors of these 25 works present and advocate recent achievements of their research related to the field of pattern recognition

Methods of navigation: An introduction to technological navigation

Ihminen on historian aikana aina navigoinut. Teknologinen navigointi syntyi merenkulussa, koska avomerellä tarvittiin mittauksia oman sijainnin määrittämiseksi. Lentokoneet, ohjukset ja avaruusalukset sekä kuivalla maalla liikkuvat kulkuneuvot ja jopa jalankulkijat kaikki ”navigoivat” nykyteknologioiden avulla. Kehitys on pääosin kahden teknologian ansiota: satelliittipaikannuksen, kuten GPS:n (Global Positioning System), ja inertianavigoinnin. Myös tieto- ja viestintätekniikka on kehittynyt, erityisesti rekursiivinen lineaarinen suodatus eli Kalmanin suodin. Lisäksi pienet ja hinnaltaan huokeat digitaaliset anturit ovat mullistamassa jokapäiväisen navigoinnin. Tässä kirjassa käsiteltäviä aiheita ovat navigoinnin perusteet, stokastiset prosessit, Kalmanin suodin, inertianavigoinnin teknologiat ja menetelmät, GNSS-signaalien rakenne, kantoaallon vaihemittaukset ja kokonaistuntemattomat, tosiaikainen GNSSpaikannus ja navigointi, differentiaalikorjausten viestintäratkaisut ja standardit, GNSStukiasemat ja -verkot, satelliittipohjaiset parannusjärjestelmät, ilmagravimetria sekä anturifuusio ja sattuman anturit.Historically, humankind has always navigated. Technological navigation originated in seafaring, because on the open ocean, measurements are needed in order to determine one’s own location as a part of navigation. Aircraft, rockets and spacecraft as well as vehicles moving on dry land, and even pedestrians, all ”navigate” by means of modern technologies. This development is mainly due to two technologies: satellite positioning, such as GPS (the Global Positioning System) and inertial navigation. Also information and communication technologiy has evolved: especially recursive linear filtering or the Kalman filter. Furthermore, small and inexpensive digital sensors are revolutionising everyday navigation. Subjects explained in this book are the fundamentals of navigation, stochastic processes, the Kalman filter, inertial navigation technology and methods, GNSS signal structure, carrier-phase measurement and ambiguities, real-time GNSS positioning and navigation, communication solutions and standards for differential corrections, GNSS base stations and networks, satellite-based augmentation systems, airborne gravimetry, sensor fusion and sensors of opportunity