3,190 research outputs found

    Scaling Properties of Ge-SixGe1-x Core-Shell Nanowire Field Effect Transistors

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    We demonstrate the fabrication of high-performance Ge-SixGe1-x core-shell nanowire field-effect transistors with highly doped source and drain, and systematically investigate their scaling properties. Highly doped source and drain regions are realized by low energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the nanowire resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and ON/OFF current ratio.Comment: 5 pages, 4 figures. IEEE Transactions on Electron Devices (in press

    Photo-FETs: phototransistors enabled by 2D and 0D nanomaterials

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    The large diversity of applications in our daily lives that rely on photodetection technology requires photodetectors with distinct properties. The choice of an adequate photodetecting system depends on its application, where aspects such as spectral selectivity, speed, and sensitivity play a critical role. High-sensitivity photodetection covering a large spectral range from the UV to IR is dominated by photodiodes. To overcome existing limitations in sensitivity and cost of state-of-the-art systems, new device architectures and material systems are needed with low-cost fabrication and high performance. Low-dimensional nanomaterials (0D, 1D, 2D) are promising candidates with many unique electrical and optical properties and additional functionalities such as flexibility and transparency. In this Perspective, the physical mechanism of photo-FETs (field-effect transistors) is described and recent advances in the field of low-dimensional photo-FETs and hybrids thereof are discussed. Several requirements for the channel material are addressed in view of the photon absorption and carrier transport process, and a fundamental trade-off between them is pointed out for single-material-based devices. We further clarify how hybrid devices, consisting of an ultrathin channel sensitized with strongly absorbing semiconductors, can circumvent these limitations and lead to a new generation of highly sensitive photodetectors. Recent advances in the development of sensitized low-dimensional photo-FETs are discussed, and several promising future directions for their application in high-sensitivity photodetection are proposed.Peer ReviewedPostprint (author's final draft

    Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations

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    Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations

    Gate-controlled reversible rectifying behaviour in tunnel contacted atomically-thin MoS2_{2} transistor

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    Atomically-thin 2D semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their full acceptance as compliant materials for integration in logic devices. Two key-components to master are the barriers at metal/semiconductor interfaces and the mobility of the semiconducting channel, which endow the building-blocks of pn{pn} diode and field effect transistor. Here, we have devised a reverted stacking technique to intercalate a wrinkle-free h-BN tunnel layer between MoS2_{2} channel and contacting electrodes. Vertical tunnelling of electrons therefore makes it possible to suppress the Schottky barriers and Fermi level pinning, leading to homogeneous gate-control of the channel chemical potential across the bandgap edges. The observed unprecedented features of ambipolar pn{pn} to np{np} diode, which can be reversibly gate tuned, paves the way for future logic applications and high performance switches based on atomically thin semiconducting channel.Comment: 23 pages, 5 main figures + 9 SI figure
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