Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

ESD circuit design and measurement techniques

Part 1 of this thesis presents a method to measure sub-nanosecond reverse recovery in wafer-level test structures. The setup uses a transmission line pulse generator with a time domain through connection to measure the device under test current. The setup is then used to measure reverse recovery in a 65 nm CMOS ESD diode, and it is found that a quasi-static compact model does not accurately describe the observed transient. A non-quasi-static charge control model is used to accurately simulate both the reverse recovery and forward bias behavior. Part 2 of this thesis reports the design and fabrication of an active feedback based high-voltage tolerant power clamp with optimally biased positive and negative feedback to bypass the trade-off between ESD performance and mis-trigger immunity. The circuit was fabricated in 28 nm CMOS, and characterization results show a 70% improvement in failure current over previous designs while maintaining mis-trigger immunity

Etude de la robustesse d'amplificateurs embarqués dans des applications portables soumis à des décharges électrostatiques (ESD) au niveau système

Avec les évolutions technologiques, les composants électroniques deviennent de plus en plus sensibles aux décharges électrostatiques (ESD). De nos jours, la fiabilité des circuits intégrés dans les étapes de fabrication est garantie par un ensemble de normes définissant des niveaux de robustesse. Mais les stratégies de protection implémentées dans les circuits intégrés, visant à respecter ces normes, ne suffisent pas toujours à garantir la robustesse des composants dans leur application finale. Ces nouveaux problèmes de fiabilité ne sont pas encore bien compris, étant donnée la complexité des phénomènes mis en jeu dans un système réel en fonctionnement. En tenant compte de ces faits, nous pouvons nous interroger sur l'efficacité des stratégies de protection contre les ESD utilisées de façon conventionnelle pour protéger contre des stress de type système. L'ensemble des travaux de thèse présentés vise à l'amélioration de la robustesse, quant à ces nouvelles exigences, de composants analogiques dédiés aux applications portables (téléphonie, multimédia). En partant d'un cas concret, pour lequel il existe une grande différence de robustesse entre le produit alimenté et non-alimenté, nous présenterons les différents résultats d'analyse (analyse de défaillance, caractérisation électrique en impulsion de type TLP et VFTLP, simulations de type SPICE) qui nous ont conduits à proposer une solution de protection intégrée respectant les exigencesWith improvement in electronic technology shrinking, electronic components are increasingly becoming sensitive to ElectroStatic Discharge (ESD). Nowadays, the reliability of integrated circuits in the manufacturing field are guaranteed by a set of standards that define levels of robustness. Nevertheless the protection strategies implemented in integrated circuits, designed to meet these standards, are not always enough to ensure the robustness of the components in their final application. The new reliability problems are not well understood, given the complexity of the phenomena involved in real systems in operation. Taking into account these facts, we can question the effectiveness of the strategies used to protect against " classical ESD " and system-type stresses. All the work presented in this thesis aims to improve the robustness with respect to these new requirements, in the case study of analog components dedicated to portable applications (telephony, multimedia). Starting from a concrete case, for which there is a large difference in the system ESD robustness between the biased and unbiased product, we will present the various results of analysis (failure analysis, electrical characterization by impulse like TLP VFTLP, SPICE-type simulations) that led us to the proposal of an integrated security solution that meets the requirement

NOTIFICATION !!!

All the content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition

NOTIFICATION !!!

All the content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition

NOTIFICATION !!!

All the content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition

NOTIFICATION!!!

The full content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition

NOTIFICATION !!!

All the content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition

NOTIFICATION !!!

All the content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition

NOTIFICATION !!!

All the content of this special edition is retrieved from the conference proceedings published by the European Scientific Institute, ESI. http://eujournal.org/index.php/esj/pages/view/books The European Scientific Journal, ESJ, after approval from the publisher re publishes the papers in a Special edition