Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects

CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology

Understanding the Mechanism of Electronic Defect Suppression Enabled by Nonidealities in Atomic Layer Deposition.

Silicon germanium (SiGe) is a multifunctional material considered for quantum computing, neuromorphic devices, and CMOS transistors. However, implementation of SiGe in nanoscale electronic devices necessitates suppression of surface states dominating the electronic properties. The absence of a stable and passive surface oxide for SiGe results in the formation of charge traps at the SiGe-oxide interface induced by GeOx. In an ideal ALD process in which oxide is grown layer by layer, the GeOx formation should be prevented with selective surface oxidation (i.e., formation of an SiOx interface) by controlling the oxidant dose in the first few ALD cycles of the oxide deposition on SiGe. However, in a real ALD process, the interface evolves during the entire ALD oxide deposition due to diffusion of reactant species through the gate oxide. In this work, this diffusion process in nonideal ALD is investigated and exploited: the diffusion through the oxide during ALD is utilized to passivate the interfacial defects by employing ozone as a secondary oxidant. Periodic ozone exposure during gate oxide ALD on SiGe is shown to reduce the integrated trap density (Dit) across the band gap by nearly 1 order of magnitude in Al2O3 (<6 × 1010 cm-2) and in HfO2 (<3.9 × 1011 cm-2) by forming a SiOx-rich interface on SiGe. Depletion of Ge from the interfacial layer (IL) by enhancement of volatile GeOx formation and consequent desorption from the SiGe with ozone insertion during the ALD growth process is confirmed by electron energy loss spectroscopy (STEM-EELS) and hypothesized to be the mechanism for reduction of the interfacial defects. In this work, the nanoscale mechanism for defect suppression at the SiGe-oxide interface is demonstrated, which is engineering of diffusion species in the ALD process due to facile diffusion of reactant species in nonideal ALD

Advanced modeling for end-of-the-roadmap CMOS and potential beyond-CMOS applications

End-of-the-roadmap CMOS devices are explored via particle-based ensemble semi-classical Monte Carlo (MC) methods employing quantum corrections (QCs) to address quantum confinement and degenerate carrier populations. The significance of such QCs is illustrated through simulation of n-channel III-V and Si FinFETs. Original contributions include our treatment of far-from-equilibrium degenerate statistics and QC-based modeling of surface-roughness scattering, as well as considering quantum-confined phonon and ionized-impurity scattering in 3D. Typical MC simulations approximate degenerate carrier populations as Fermi distributions to model the Pauli-blocking (PB) of scattering to occupied final states. To allow for increasingly far-from-equilibrium non-Fermi carrier distributions in ultra-scaled and III-V devices, we instead generate the final-state occupation probabilities used for PB by sampling the local carrier populations as a function of energy and energy valley. This process is aided by the use of fractional carriers or sub-carriers, which minimizes classical carrier-carrier scattering. Quantum confinement effects are addressed through quantum-correction potentials (QCPs) generated from coupled Schrödinger-Poisson solvers, as commonly done. However, we use our valley- and orientation-dependent QCPs not just to redistribute carriers in real space, or even among energy valleys, but also to calculate confinement-dependent phonon, ionized-impurity, and surface-roughness scattering rates. Collectively, these quantum effects can substantially reduce and even eliminate otherwise expected benefits of considered InGaAs FinFETs over otherwise identical Si FinFETs, despite higher thermal velocities in InGaAs. Beyond-CMOS device concepts are also being considered for future applications. Thin-film sub-5 nm magnetic skyrmions constitute an ultimate scaling alternative for beyond-CMOS data storage technologies. These robust non-collinear spin-textures can be moved and manipulated by spin-polarized or non-spin-polarized electrical currents, which is extremely attractive for integration with current memory technologies. An innovative technique to detect isolated nano-skyrmions with a current-perpendicular-to-plane is shown, which has immediate implications for device concepts. Such a mechanism is explored by studying the atomistic electronic structure of the magnetic quasiparticles. The tunneling conductance is quite sensitive to spatial variations in the electronic structure, as a large atomistic conductance anisotropy up to 20 is found for magnetic skyrmions in Pd/Fe/Ir(111) magnetic thin-films. This spin-mixing magnetoresistance effect possibly could be incorporated in future magnetic storage technologies.Electrical and Computer Engineerin

핀펫 소자에서의 핫캐리어 신뢰성 분석

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 신형철.CMOS 로직 소자는 퍼포먼스를 향상시키기 위해 지속적으로 축소화 되고 있다. 하지만 구조 파라미터들의 축소화에 비해 동작 전압은 충분히 감소하지 않는다. 따라서 소자 내 수직 전계나 온도가 증가하는 추세이기 때문에 신뢰성은 계속해서 문제가 되고 있다. 최근 3D 소자의 신뢰성에 대한 연구는 많이 진행되고 있지만 empirical 모델링과 관련된 연구가 대부분이다. 따라서 본 연구에서는 실제 측정을 기반으로 시뮬레이션을 이용하여 물리적 이론 중심으로 로직 소자의 핫캐리어 신뢰성을 분석하였다. 먼저 핫캐리어 모델의 정확성을 향상시키기 위해서 TCAD 시뮬레이션에 electron-electron scattering을 적용하였다. 추가적으로 3D FinFET의 측정 데이터와 calibration을 진행하여 모델의 정합성을 확인하였다. calibration 과정에서는 모든 scattering 메커니즘을 고려하기 위해 다양한 전압과 온도 조건이 필요하다. 따라서 다양한 전압 조건에 따른 HCD를 분석하고, calibration을 진행하여 HCD 모델의 파라미터를 추출하였다. 다음으로 전압 조건에 따른 HCD의 온도 경향성을 분석하였다. oxide trap과 달리 interface trap은 전압 조건에 따라 다른 온도 경향성을 보인다. 따라서 interface trap을 3가지 성분으로 분리하여 각 성분의 온도 경향성을 분석하였다. Multiple particle process(MP)과 field enhanced thermal degradation process(FP)는 전압 조건과 상관없이 일정한 온도 경향성을 가진다. 반면 Single particle process(SP)는 scattering의 영향을 받기 때문에 온도 경향성은 전압 조건에 따라 달라진다. 온도 경향성 분석 과정에서도 calibration을 진행하며 여러 번의 iteration을 통해 다양한 전압 및 온도가 고려된 파라미터를 추출한다. 추출된 파라미터를 적용한 시뮬레이션 모델은 기존의 모델보다 더 정확하게 HCD 측정 결과를 예측하였다. 결과적으로 물리적 이론에 근거하여 시뮬레이션 모델 구축함으로써 HCD 분석의 정확성을 향상시켰다. 하지만 가속 조건과 동작 조건의 self-heating 효과가 다르기 때문에 소자가 실제 CMOS 회로의 동작 조건에서 interface trap을 발생시키는 메커니즘은 다를 수 있다. 따라서 우리는 동작 영역에서의 각 성분의 비율까지 예측하였다. 마지막으로 우리는 10 nm node 소자에서 nFinFET에 비해 pFinFET에서 높은 열화가 발생하는 원인에 대해 분석하였다. pFinFET은 소스/드레인 물질로 SiGe를 사용하기 때문에 nFinFET에 비해 self-heating 효과가 심하여 소자 온도가 도 높다. 이론적으로 MP 메커니즘의 lifetime은 온도가 증가할수록 감소하기 때문에 MP에 의한 열화 또한 감소한다. 따라서 소자 온도가 더 높은 pFinFET에서 nFinFET에 비해 더 많은 MP가 발생하기 어렵다. 하지만 nFinFET 과 달리 pFinFET에서는 Si-H bond의 electron과 hole이 반응하여 interface trap을 생성시키는 RD 가 발생할 수 있다. 또한 RD는 온도가 높을수록 더 많은 열화가 발생하기 때문에, pFinFET에서 nFinFET보다 더 많은 열화가 발생하는 현상을 설명할 수 있다. 따라서 우리는 HCD 조건이지만 소자 온도가 높은 pFinFET에서 추가적인 RD 메커니즘이 발생할 수 있다고 제안한다. 다양한 전압 조건에서의 전류 열화율을 통해 주요 열화 메커니즘을 분석하였으며 pFinFET에서는 RD가 주요함을 확인하였다. 또한 TCAD 시뮬레이션을 이용하여 HCD 조건에서 발생할 수 있는 RD를 예측하였다. 그 결과 RD를 제외한 순수 hot carrier 성분은 pFinFET보다 nFinFET에서 더 많이 발생한다.CMOS logic devices have been scaled down to improve performance. However, the operating voltage is not sufficiently reduced compared to the scale down in physical dimensions. Therefore, since the electric field and temperature of the device gradually increase, reliability is still a critical issue in logic devices. Recently, many studies on the reliability of 3D devices are being conducted, but most of the studies are related to empirical modeling. Therefore, in this study, based on the actual measurement results, the hot carrier degradation(HCD) reliability of the logic device was analyzed focusing on the physical theory using Technology computer-aided design (TCAD) simulation. First, electron-electron scattering(EES) was applied to the TCAD simulation to improve the accuracy of the hot carrier model. Additionally, calibration between the measurement data of 14 nm node FinFET and the model was performed to confirm the consistency. The calibration process required various voltage and temperature conditions to account for all scattering mechanisms. Therefore, HCD was analyzed according to various voltage conditions, and the parameters of the HCD model were extracted by calibration process. Next, temperature dependence under various HCD conditions was analyzed. Unlike oxide traps, interface traps show different temperature dependence depending on HCD voltage conditions. Therefore, the interface traps were separated into three components and the temperature dependence was analyzed for each component. Multiple particle process (MP) and Field enhanced thermal degradation process (FP) have a constant temperature dependence regardless of voltage conditions. On the other hand, the temperature dependence of Single particle process (SP) varies depending on the voltage condition because SP is affected by scattering. In the process of temperature dependence analysis, calibration is also performed and parameters considering various voltages and temperatures were extracted through several iterations. The improved model to which the extracted parameters were applied showed more precise prediction of degradation compared to that of the previous model. As a results, accuracy of the HCD analysis was improved by establishing the HCD simulation framework based on physical theories. However, since the self-heating effect of the acceleration condition and the operation condition are different, the HCD mechanism that occurs in the actual CMOS circuit may also be different. Therefore, we predicted the ratio of each component under operating condition. Finally, in 10 nm node devices, we analyzed the cause of higher HCD in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain material which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle(MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the HCD mechanisms to occur more in pFinFETs which has higher temperature than nFinFETs. However, in pFinFETs unlike nFinFETs, reaction-diffusion (RD) mechanism can occur in which holes react with the electrons of Si-H bonds to generate interface traps. Also, since RD deteriorates more as the temperature increases, the phenomenon that more degradation occurs in pFinFET than nFinFET can be explained by the RD mechanism. Therefore, we propose an additional RD mechanism that is caused by high device temperature in pFinFETs even in HCD condition. Main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that RD is dominant in pFinFETs. Also, RD that can occur in HCD condition was predicted through TCAD simulation. As a results, degradation due to pure hot carriers without RD occurs more in nFinFETs than in pFinFETs.Abstract i Chapter 1. Introduction 1 Chapter 2. Hot Carrier Degradation Model 4 2.1. Physical theory 4 2.2. TCAD simulation 8 2.3. Calibration process 14 2.4. Summary 22 Chapter 3. Analysis on Temperature Dependence of HCD 25 3.1. Introduction 25 3.2. Temperature dependence according to acceleration conditions 26 3.3. Calibration process 30 3.4. Mechanism separation 33 3.5. HCD prediction in the nominal voltage 35 3.6. Summary 36 Chapter 4. Comparative Analysis of HCD in nMOS/pMOS FinFET 39 4.1. Introduction 39 4.2. Comparison of HCD in the long/short channel FinFET 40 4.3. Self-heating effect in n/pFinFET 44 4.4. Bias Temperature Instability(BTI) in n/pFinFET 47 4.5. Summary 59 Chapter 5. Conclusion 64 Abstract in Korean 66 List of Publications 69Docto

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO2 was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA). MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO2/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (Rs) associated with the substrate and metal contact. The interface state density (Dit), calculated by conductance method, suggests that Dit is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit whereas crystallized HfO2 has the highest Dit. Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples. The reliability of TiN/ZrO2/Al2O3/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO2 by SPAO when SPAO is processed after high-k. GeO2 at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress. To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces