A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors&apos; field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (<i>V</i>_<i>GS</i>=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. </p><p style=&quot;line-height: 20px;&quot;> We propose a <b>S</b>elf-<b>B</b>iasing <b>V</b>irtual <b>R</b>ails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. </p><p style=&quot;line-height: 20px;&quot;> Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability

Low Power SoC Design

The design of Low Power Systems-on-Chips (SoC) in very deep submicron technologies becomes a very complex task that has to bridge very high level system description with low-level considerations due to technology defaults and variations and increasing system and circuit complexity. This paper describes the major low-level issues, such as dynamic and static power consumption, temperature, technology variations, interconnect, DFM, reliability and yield, and their impact on high-level design, such as the design of multi-Vdd, fault-tolerant, redundant or adaptive chip architectures. Some very low power System-on-Chip (SoC) will be presented in three domains: wireless sensor networks, vision sensors and mobile TV

Impact of Device Parameteres of Triple Gate SOI-FINFET on the Performance of CMOS Inverter at 22NM

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the down scaling of the gate oxide thickness due to higher gate leakage current and gate capacitance

A Review on Enhancement of SRAM Memory Cell

In this field research paper explores the design and analysis of Static Random Access Memory (SRAMs) that focuses on optimizing delay and power. CMOS SRAM cell consumes very little power and has less read and write time. Higher cell ratios will decrease the read and write time and improve stability. PMOS semiconductor unit with fewer dimensions reduces the ability consumption. During this paper, 6T SRAM cell is implemented with reduced power and performance is good according to read and write time, delay and power consumption. It's been noticed typically that increased memory capability will increase the bit-line parasitic capacitance that successively slows down voltage sensing, to avoid this drawback use optimized scaling techniques and more, get improve performance of the design. Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major area of concern in today's memory technology. During this paper SRAM cells supported 6T, 9T, and 8T configurations are compared based on performance for reading and write operations. During this paper completely different static random access memory is designed to satisfy low power, high-performance circuit and also the extensive survey on options of various static random access memory (SRAM) designs were reported. Improve performance static random access memory based on designing a low power SRAM cell structure with optimum write access power

Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

© 2015 IEEE.Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application