Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.

Shen Jun-Hua.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 151-154).Abstracts in English and Chinese.Abstract --- p.ii摘要 --- p.ivAcknowledgments --- p.viTable of Contents --- p.viiList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1. --- Overview --- p.1Chapter 1.2. --- Motivation and Objectives --- p.5Chapter 1.3. --- Original Contributions of This Work --- p.6Chapter 1.4. --- Organization of the Thesis --- p.7Chapter Chapter 2 --- Sigma-delta Modulation and IF A/D Conversion --- p.8Chapter 2.1. --- Introduction --- p.8Chapter 2.2. --- Fundamentals of Sigma-delta Modulation --- p.9Chapter 2.2.1. --- Feedback Controlled System --- p.9Chapter 2.2.2. --- Quantization Noise --- p.11Chapter 2.2.3. --- Oversampling and Noise-shaping --- p.11Chapter 2.2.4. --- Stability --- p.15Chapter 2.2.5. --- Noise Sources --- p.17Chapter 2.2.6. --- Baseband Sigma-delta Modulation --- p.28Chapter 2.2.7. --- Bandpass Sigma-delta Modulation --- p.28Chapter 2.3. --- Discrete-time Sigma-delta Modulation --- p.29Chapter 2.4. --- Continuous-time Sigma-delta Modulation --- p.29Chapter 2.5. --- IF-input Complex Analog to Digital Converter --- p.31Chapter 2.6. --- Image Rejection --- p.32Chapter 2.7. --- Integrated Mixer --- p.36Chapter Chapter 3 --- High Level Modeling and Simulation --- p.39Chapter 3.1. --- Introduction --- p.39Chapter 3.2. --- System Level Sigma-delta Modulator Design --- p.40Chapter 3.3. --- Continuous-time NTF Generation --- p.46Chapter 3.4. --- Discrete-time Sigma-delta Modulator Modeling --- p.50Chapter 3.5. --- Continuous-time Sigma-delta Modulator Modeling --- p.52Chapter 3.6. --- Modeling of Nonidealities --- p.53Chapter 3.7. --- High Level Simulation Results --- p.58Chapter Chapter 4 --- Transistor Level Implementation of the Complex Modulator and Layout --- p.65Chapter 4.1. --- Introduction --- p.65Chapter 4.2. --- IF Input Complex Modulator --- p.65Chapter 4.3. --- High IR IF Input Complex Modulator Design --- p.67Chapter 4.4. --- System Design --- p.73Chapter 4.5. --- Building Blocks Design --- p.77Chapter 4.5.1. --- Transconductor Design --- p.77Chapter 4.5.2. --- RC Integrator Design --- p.87Chapter 4.5.3. --- Gm-C Integrator Design --- p.90Chapter 4.5.4. --- Voltage to Current Converter --- p.95Chapter 4.5.5. --- Current Comparator Design --- p.96Chapter 4.5.6. --- Dynamic Element Matching Design --- p.98Chapter 4.5.7. --- Mixer Design --- p.100Chapter 4.5.8. --- Clock Generator --- p.103Chapter 4.6. --- Transistor Level Simulation of the Design --- p.106Chapter 4.7. --- Layout of the Mixed Signal Design --- p.109Chapter 4.7.1. --- Layout Overview --- p.109Chapter 4.7.2. --- Capacitor layout --- p.110Chapter 4.7.3. --- Resistor Layout --- p.113Chapter 4.7.4. --- Power and Ground Routing --- p.114Chapter 4.7.5. --- OTA Layout --- p.115Chapter 4.7.6. --- Chip Layout --- p.117Chapter 4.8. --- PostLayout Simulation --- p.120Chapter 5. --- Chapter 5 Measurement Results and Improvement --- p.122Chapter 5.1. --- Introduction --- p.122Chapter 5.2. --- PCB Design --- p.123Chapter 5.3. --- Test Setup --- p.125Chapter 5.4. --- Measurement of SNR and IRR --- p.128Chapter 5.5. --- Discussion of the Chip Performance --- p.131Chapter 5.6. --- Design of Robust Sigma Delta Modulator --- p.139Chapter Chapter 6 --- Conclusion --- p.148Chapter 6.1. --- Conclusion --- p.148Chapter 6.2. --- Future Work --- p.150Bibliography --- p.151Appendix A Schematics of Building Blocks --- p.155Author's Publications --- p.15

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)