A Scalable Four-Channel Frequency-Division Multiplexing MIMO Radar Utilizing Single-Sideband Delta-Sigma Modulation

A scalable four-channel multiple-input multiple-output (MIMO) radar that features a modular system architecture and a novel frequency-division multiplexing approach is presented in this article. It includes a single 30-GHz voltage-controlled oscillator (VCO) for the local oscillator signal generation, four cascaded 120-GHz transceivers with a frequency quadrupler, and on-board differential series-fed patch antennas. The utilized uniform antenna configuration results in 16 virtual array elements and enables an angular resolution of 6.2°. The vector modulators in the transmit (TX) paths allow the application of complex bit streams of second-order delta-sigma modulators easily generated on a field-programmable gate array (FPGA) to implement single-sideband (SSB) modulation on the TX signals resulting in orthogonal waveforms for the MIMO operation. Only one phase-locked loop and no digital-To-Analog converter is required. The waveform diversity also allows the simultaneous transmission of the TX signals to reduce the measurement time. The application of the SSB modulation on the frequency-modulated continuous-wave MIMO radar requires only half of the intermediate frequency bandwidth compared with the double-sideband modulation. The issue of the phase and amplitude mismatches at the virtual array elements due to the scalable radar architecture is addressed and a calibration solution is introduced in this article. Radar measurements using different numbers of virtual array elements were compared and the digital-beamforming method was applied to the results to create 2-D images. © 1963-2012 IEEE

A CMOS Digital Beamforming Receiver

As the demand for high speed communication is increasing, emerging wireless techniques seek to utilize unoccupied frequency ranges, such as the mm-wave range. Due to high path loss for higher carrier frequencies, beamforming is an essential technology for mm-wave communication. Compared to analog beamforming, digital beamforming provides multiple simultaneous beams without an SNR penalty, is more accurate, enables faster steering, and provides full access to each element. Despite these advantages, digital beamforming has been limited by high power consumption, large die area, and the need for large numbers of analog-to-digital converters. Furthermore, beam squinting errors and ADC non-linearity limit the use of large digital beamforming arrays. We address these limitations. First, we address the power and area challenge by combining Interleaved Bit Stream Processing (IL-BSP) with power and area efficient Continuous-Time Band-Pass Delta-Sigma Modulators (CTBPDSMs). Compared to conventional DSP, IL-BSP reduces both power and area by 80%. Furthermore, the new CTBPDSM architecture reduces ADC area by 67% and the energy per conversion by 43% compared to previous work. Second, we introduce the first integrated digital true-time-delay digital beamforming receiver to resolve the beam squinting. True-time-delay beamforming eliminates squinting, making it an ideal choice for large-array wide-bandwidth applications. Third, we present a new current-steering DAC architecture that provides a constant output impedance to improve ADC linearity. This significantly reduces distortion, leading to an SFDR improvement of 13.7 dB from the array. Finally, we provide analysis to show that the ADC power consumption of a digital beamformer is comparable to that of the ADC power for an analog beamformer. To summarize, we present a prototype phased array and a prototype timed array, both with 16 elements, 4 independent beams, a 1 GHz center frequency, and a 100 MHz bandwidth. Both the phased array and timed array achieve nearly ideal conventional and adaptive beam patterns, including beam tapering and adaptive nulling. With an 11.2 dB array gain, the phased array achieves a 58.5 dB SNDR over a 100 MHz bandwidth, while consuming 312 mW and occupying 0.22 mm2. The timed array achieves an EVM better than -37 dB for 5 MBd QAM-256 and QAM-512, occupies only 0.29 mm2, and consumes 453 mW.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147716/1/smjang_1.pd

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

This document is the Accepted Manuscript version of the following article: Junfeng Zhang, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang, and Baoyong Chi, ‘A 10-b Fourth-Order Quadrature Bandpass Continuous-Time ΣΔ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver’, IEEE Transactions on Microwave Theory and Practice, Vol. 65 (4): 1303-1314, first published online 16 February 2017. The version of record is available online at DOI: 10.1109/TMTT.2017.266237, Published by IEEE. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A fourth-order quadrature bandpass continuous-time sigma-delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital-analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.Peer reviewe

Linear Operation of Switch-Mode Outphasing Power Amplifiers

Radio transceivers are playing an increasingly important role in modern society. The ”connected” lifestyle has been enabled by modern wireless communications. The demand that has been placed on current wireless and cellular infrastructure requires increased spectral efficiency however this has come at the cost of power efficiency. This work investigates methods of improving wireless transceiver efficiency by enabling more efficient power amplifier architectures, specifically examining the role of switch-mode power amplifiers in macro cell scenarios. Our research focuses on the mechanisms within outphasing power amplifiers which prevent linear amplification. From the analysis it was clear that high power non-linear effects are correctable with currently available techniques however non-linear effects around the zero crossing point are not. As a result signal processing techniques for suppressing and avoiding non-linear operation in low power regions are explored. A novel method of digital pre-distortion is presented, and conventional techniques for linearisation are adapted for the particular needs of the outphasing power amplifier. More unconventional signal processing techniques are presented to aid linearisation of the outphasing power amplifier, both zero crossing and bandwidth expansion reduction methods are designed to avoid operation in nonlinear regions of the amplifiers. In combination with digital pre-distortion the techniques will improve linearisation efforts on outphasing systems with dynamic range and bandwidth constraints respectively. Our collaboration with NXP provided access to a digital outphasing power amplifier, enabling empirical analysis of non-linear behaviour and comparative analysis of behavioural modelling and linearisation efforts. The collaboration resulted in a bench mark for linear wideband operation of a digital outphasing power amplifier. The complimentary linearisation techniques, bandwidth expansion reduction and zero crossing reduction have been evaluated in both simulated and practical outphasing test benches. Initial results are promising and indicate that the benefits they provide are not limited to the outphasing amplifier architecture alone. Overall this thesis presents innovative analysis of the distortion mechanisms of the outphasing power amplifier, highlighting the sensitivity of the system to environmental effects. Practical and novel linearisation techniques are presented, with a focus on enabling wide band operation for modern communications standards

Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

Low Power Continuous-time Bandpass Delta-Sigma Modulators.

Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW. Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators. The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd