Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing

Online Training of Spiking Recurrent Neural Networks with Phase-Change Memory Synapses

Spiking recurrent neural networks (RNNs) are a promising tool for solving a wide variety of complex cognitive and motor tasks, due to their rich temporal dynamics and sparse processing. However training spiking RNNs on dedicated neuromorphic hardware is still an open challenge. This is due mainly to the lack of local, hardware-friendly learning mechanisms that can solve the temporal credit assignment problem and ensure stable network dynamics, even when the weight resolution is limited. These challenges are further accentuated, if one resorts to using memristive devices for in-memory computing to resolve the von-Neumann bottleneck problem, at the expense of a substantial increase in variability in both the computation and the working memory of the spiking RNNs. To address these challenges and enable online learning in memristive neuromorphic RNNs, we present a simulation framework of differential-architecture crossbar arrays based on an accurate and comprehensive Phase-Change Memory (PCM) device model. We train a spiking RNN whose weights are emulated in the presented simulation framework, using a recently proposed e-prop learning rule. Although e-prop locally approximates the ideal synaptic updates, it is difficult to implement the updates on the memristive substrate due to substantial PCM non-idealities. We compare several widely adapted weight update schemes that primarily aim to cope with these device non-idealities and demonstrate that accumulating gradients can enable online and efficient training of spiking RNN on memristive substrates

Design of CMOS-memristor Circuits for LSTM architecture

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model

A Review of Graphene-Based Memristive Neuromorphic Devices and Circuits

As data processing volume increases, the limitations of traditional computers and the need for more efficient computing methods become evident. Neuromorphic computing mimics the brain's low-power and high-speed computations, making it crucial in the era of big data and artificial intelligence. One significant development in this field is the memristor, a device that exhibits neuromorphic tendencies. The performance of memristive devices and circuits relies on the materials used, with graphene being a promising candidate due to its unique properties. Researchers are investigating graphene-based memristors for large-scale, sustainable fabrication. Herein, progress in the development of graphene-based memristive neuromorphic devices and circuits is highlighted. Graphene and its common fabrication methods are discussed. The fabrication and production of graphene-based memristive devices are reviewed and comparisons are provided among graphene- and nongraphene-based memristive devices. Next, a detailed synthesis of the devices utilizing graphene-based memristors is provided to implement the basic building blocks of neuromorphic architectures, that is, synapses, and neurons. This is followed by reviewing studies building graphene memristive spiking neural networks (SNNs). Finally, insights on the prospects of graphene-based neuromorphic memristive systems including their device- and network-level challenges and opportunities are given

Hierarchical Temporal Memory using Memristor Networks: A Survey

This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed