Model Transformations from a Data Parallel Formalism towards Synchronous Languages

The increasing complexity of embedded system designs calls for high-level specification formalisms and for automated transformations towards lower-level descriptions. In this report, a metamodel and a transformation chain are defined from a high-level modeling framework, Gaspard, for data-parallel systems towards a formalism of synchronous equations. These equations are translated in synchronous data-flow languages, such as Lustre, Lucid synchrone and Signal, which provide designers with formal techniques and tools for validation. In order to benefit from the methodological advantages of re-usability and platform-independence, a Model-Driven Engineering approach is applied

Adaptivity in High-Performance Embedded Systems: a Reactive Control Model for Reliable and Flexible Design

International audienceSystem adaptivity is increasingly demanded in high-performance embedded systems, particularly in multimedia System-on-Chip (SoC), due to growing Quality of Service requirements. This paper presents a reactive control model that has been introduced in Gaspard, our framework dedicated to SoC hardware/software co-design. This model aims at expressing adaptivity as well as reconfigurability in systems performing data-intensive computations. It is generic enough to be used for description in the different parts of an embedded system, e.g. specification of how different data-intensive algorithms can be chosen according to some computation modes at the functional level; expression of how hardware components can be selected via the usage of a library of Intellectual Properties (IPs) according to execution performances. The transformation of this model towards synchronous languages is also presented, in order to allow an automatic code generation usable for formal verification, based of techniques such as model checking and controller synthesis as illustrated in the paper. This work, based on Model-Driven Engineering and the standard UML MARTE profile, has been implemented in Gaspard

Model-oriented co-design of homogeneous computing systems

This article proposes an approach to the construction of a technological platform for designing function-oriented processors (FOP) built on the basis of homogeneous computing environments (OVS). A feature of the proposed approach is the use of co-design - a simultaneous and interconnected design of hardware (HW) and software (SW) FOP components. The paper presents proposals for the implementation of this approach, based on the use of the prin-ciple of model-based design, which allows you to make the co-design process iterative and effectively distribute data processing procedures between HW and SW - components of FOP. Based on the consideration of the experience in implementing such solutions, the paper presents the composition of functional subsystems of technological platforms, a diagram of information interaction between these subsystems based on intensive using of web-technologies at all stages of the design and operation of FOP. © 2019 Tomsk State University. All rights reserved

Modeling of Topologies of Interconnection Networks based on Multidimensional Multiplicity

Modern SoCs are becoming more complex with the integration of heterogeneous components (IPs). For this purpose, a high performance interconnection medium is required to handle the complexity. Hence NoCs come into play enabling the integration of more IPs into the SoC with increased performance. These NoCs are based on the concept of Interconnection networks used to connect parallel machines. In response to the MARTE RFP of the OMG, a notation of multidimensional multiplicity has been proposed which permits to model repetitive structures and topologies. This report presents a modeling methodology based on this notation that can be used to model a family of Interconnection Networks called Delta Networks which in turn can be used for the construction of NoCs

MARTE based design flow for Partially Reconfigurable Systems-on-Chips

International audienceSystems-on-Chip (SoCs) are considered an integral solution for designing embedded systems, for targeting complex intensive parallel computation applications. As advances in SoC technology permit integration of increasing number of hardware resources on a single chip, the targeted application domains such as software-defined radio are become increasingly sophisticated. The fallout of this complexity is that the system design, particularly software design, does not evolve at the same pace as that of hardware leading to a significant productivity gap. Adaptivity and reconfigurability are also critical issues for SoCs which must be able to cope with end user environment and requirements

Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs

International audienceThe number of integrated transistors that can be contained on a chip are increasing at an exponential rate, along with rise in targeted sophisticated applications. Thus the design of Systems-on-Chip (SoC) is becoming more and more complex. Hence there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. This paper presents a novel approach for expressing system adaptivity and reconfigurability in Gaspard, a SoC co-design framework, with special focus on partially dynamically reconfigurable FPGAs. The framework is compliant with UML MARTE profile proposed by Object Management Group, for modeling and analysis of realtime embedded systems. The overall objective is to carry out system modeling at a high abstraction level expressed in UML; and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesi

Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation

International audienceAs SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs

Array-OL Revisited, Multidimensional Intensive Signal Processing Specification

This paper presents the Array-OL specification language. It is a high-level visual language dedicated to multidimensional intensive signal processing applications. It allows to specify both the task parallelism and the data parallelism of these applications on focusing on their complex multidimensional data access patterns. This presentation includes several extensions and tools developed around Array-OL during the last few years and discusses the mapping of an Array-OL specification onto a distributed heterogeneous hardware architecture

Models for Co-Design of Heterogeneous Dynamically Reconfigurable SoCs

International audienceThe design of Systems-on-Chip is becoming an increasing difficult challenge due to the continuous exponential evolution of the targeted complex architectures and applications. Thus, seamless methodologies and tools are required to resolve the SoC design issues. This chapter presents a high level component based approach for expressing system reconfigurability in SoC co-design. A generic model of reactive control is presented for Gaspard2, a SoC co-design framework. Control integration in different levels of the framework is explored along with a comparison of their advantages and disadvantages. Afterwards, control integration at another high abstraction level is investigated which proves to be more beneficial then the other alternatives. This integration allows to integrate reconfigurability features in modern SoCs. Finally a case study is presented for validation purposes. The presented works are based on Model-Driven Engineering (MDE) and UML MARTE profile for modeling and analysis of real-time embedded systems

Augmented graphic thinking in Geometry: developable architectural surfaces in experimental pavilions

We will analyze how the incorporation of digital manufacturing in our schools is motivating a deep reflection about the need to be familiar with both the foundations of geometry as well as with more advanced knowledge. The reinterpretation of our inherited graphic design discipline in light of current digital tools can open up new fields of study and work, such as is occurring in the field of developable surfaces, warped surfaces and many others. In addition, through non-linear graphic processes and digital tools of parametric design, we can arrive at an "expanded graphic thinking" that we can place at the service of production and morphological research. Thus, the old descriptive geometry - geometry based on graphics – comes to serve a cybernetically enlarged mind. We will present four experimental pavilions resulting from several workshops on geometry and digital manufacturing carried out in collaboration between the University of Seville and several Ibero-American Universities. Based on the deep geometric knowledge of developable helical surfaces and surfaces of equal slope, a guided exercise is proposed to approach the design, manufacturing and assembly phases of these architectural installations on a real scale