Cybersecurity Methods for Grid-Connected Power Electronics

The present work shows a secure-by-design process, defense-in-depth method, and security techniques for a secure distributed energy resource. The distributed energy resource is a cybersecure, solar inverter and battery energy storage system prototype, collectively called the Cybersecure Power Router. Consideration is given to the use of the Smart Green Power Node for a foundation of the present work. Metrics for controller security are investigated to evaluate firmware security techniques. The prototype\u27s ability to mitigate, respond to, and recover from firmware integrity degradation is examined. The prototype shows many working security techniques within the context of a grid-connected, distributed energy resource. Further work is expected in the Cybersecure Power Router project. Consideration is also provided for the migration of the present research and the Smart Green Power Node to realize a pre-production prototype

Freeze-Damage Detection in Lemons Using Electrochemical Impedance Spectroscopy

[EN] Lemon is the most sensitive citrus fruit to cold. Therefore, it is of capital importance to detect and avoid temperatures that could damage the fruit both when it is still in the tree and in its subsequent commercialization. In order to rapidly identify frost damage in this fruit, a system based on the electrochemical impedance spectroscopy technique (EIS) was used. This system consists of a signal generator device associated with a personal computer (PC) to control the system and a double-needle stainless steel electrode. Tests with a set of fruits both natural and subsequently frozen-thawed allowed us to differentiate the behavior of the impedance value depending on whether the sample had been previously frozen or not by means of a single principal components analysis (PCA) and a partial least squares discriminant analysis (PLS-DA). Artificial neural networks (ANNs) were used to generate a prediction model able to identify the damaged fruits just 24 hours after the cold phenomenon occurred, with sufficient robustness and reliability (CCR = 100%).This research was funded by the the Spanish Government/FEDER funds (RTI2018-100910-B-C43) (MINECO/FEDER) and the Conselleria d'Educacio, Investigacio, Cultura i Esport de la Generalitat Valenciana (GV/2018/090).Ochandio Fernández, A.; Olguín Pinatti, CA.; Masot Peris, R.; Laguarda-Miro, N. (2019). Freeze-Damage Detection in Lemons Using Electrochemical Impedance Spectroscopy. Sensors. 19(18):1-12. https://doi.org/10.3390/s19184051S1121918Zabihi, H., Vogeler, I., Amin, Z. M., & Gourabi, B. R. (2016). Mapping the sensitivity of citrus crops to freeze stress using a geographical information system in Ramsar, Iran. Weather and Climate Extremes, 14, 17-23. doi:10.1016/j.wace.2016.10.002Tan, E. S., Slaughter, D. C., & Thompson, J. F. (2005). Freeze damage detection in oranges using gas sensors. Postharvest Biology and Technology, 35(2), 177-182. doi:10.1016/j.postharvbio.2004.07.008Slaughter, D. C., Obenland, D. M., Thompson, J. F., Arpaia, M. L., & Margosan, D. A. (2008). Non-destructive freeze damage detection in oranges using machine vision and ultraviolet fluorescence. Postharvest Biology and Technology, 48(3), 341-346. doi:10.1016/j.postharvbio.2007.09.012Sala, J. M., Sanchez-Ballesta, M. T., Alférez, F., Mulas, M., Zacarias, L., & Lafuente, M. T. (2005). A comparative study of the postharvest performance of an ABA-deficient mutant of oranges. Postharvest Biology and Technology, 37(3), 232-240. doi:10.1016/j.postharvbio.2005.05.006Siboza, X. I., Bertling, I., & Odindo, A. O. (2014). Salicylic acid and methyl jasmonate improve chilling tolerance in cold-stored lemon fruit (Citrus limon). Journal of Plant Physiology, 171(18), 1722-1731. doi:10.1016/j.jplph.2014.05.012Jha, P. K., Xanthakis, E., Chevallier, S., Jury, V., & Le-Bail, A. (2019). Assessment of freeze damage in fruits and vegetables. Food Research International, 121, 479-496. doi:10.1016/j.foodres.2018.12.002Sala, J. M., & Lafuente, M. T. (1999). Catalase in the Heat-Induced Chilling Tolerance of Cold-Stored Hybrid Fortune Mandarin Fruits. Journal of Agricultural and Food Chemistry, 47(6), 2410-2414. doi:10.1021/jf980805eMoomkesh, S., Mireei, S. A., Sadeghi, M., & Nazeri, M. (2017). Early detection of freezing damage in sweet lemons using Vis/SWNIR spectroscopy. Biosystems Engineering, 164, 157-170. doi:10.1016/j.biosystemseng.2017.10.009Obenland, D. M., Aung, L. H., Bridges, D. L., & Mackey, B. E. (2003). Volatile Emissions of Navel Oranges as Predictors of Freeze Damage. Journal of Agricultural and Food Chemistry, 51(11), 3367-3371. doi:10.1021/jf021109oGambhir, P. N., Choi, Y. J., Slaughter, D. C., Thompson, J. F., & McCarthy, M. J. (2005). Proton spin-spin relaxation time of peel and flesh of navel orange varieties exposed to freezing temperature. Journal of the Science of Food and Agriculture, 85(14), 2482-2486. doi:10.1002/jsfa.2266Fuentes, A., Masot, R., Fernández-Segovia, I., Ruiz-Rico, M., Alcañiz, M., & Barat, J. M. (2013). Differentiation between fresh and frozen-thawed sea bream (Sparus aurata) using impedance spectroscopy techniques. Innovative Food Science & Emerging Technologies, 19, 210-217. doi:10.1016/j.ifset.2013.05.001Conesa, C., García-Breijo, E., Loeff, E., Seguí, L., Fito, P., & Laguarda-Miró, N. (2015). An Electrochemical Impedance Spectroscopy-Based Technique to Identify and Quantify Fermentable Sugars in Pineapple Waste Valorization for Bioethanol Production. Sensors, 15(9), 22941-22955. doi:10.3390/s150922941Wu, L., Ogawa, Y., & Tagawa, A. (2008). Electrical impedance spectroscopy analysis of eggplant pulp and effects of drying and freezing–thawing treatments on its impedance characteristics. Journal of Food Engineering, 87(2), 274-280. doi:10.1016/j.jfoodeng.2007.12.003Serrano-Pallicer, E., Muñoz-Albero, M., Pérez-Fuster, C., Masot Peris, R., & Laguarda-Miró, N. (2018). Early Detection of Freeze Damage in Navelate Oranges with Electrochemical Impedance Spectroscopy. Sensors, 18(12), 4503. doi:10.3390/s18124503Grossi, M., & Riccò, B. (2017). Electrical impedance spectroscopy (EIS) for biological analysis and food characterization: a review. Journal of Sensors and Sensor Systems, 6(2), 303-325. doi:10.5194/jsss-6-303-2017Chowdhury, A., Kanti Bera, T., Ghoshal, D., & Chakraborty, B. (2016). Electrical Impedance Variations in Banana Ripening: An Analytical Study with Electrical Impedance Spectroscopy. Journal of Food Process Engineering, 40(2), e12387. doi:10.1111/jfpe.12387Bauchot, A. D., Harker, F. R., & Arnold, W. M. (2000). The use of electrical impedance spectroscopy to assess the physiological condition of kiwifruit. Postharvest Biology and Technology, 18(1), 9-18. doi:10.1016/s0925-5214(99)00056-3Figueiredo Neto, A., Cárdenas Olivier, N., Rabelo Cordeiro, E., & Pequeno de Oliveira, H. (2017). Determination of mango ripening degree by electrical impedance spectroscopy. Computers and Electronics in Agriculture, 143, 222-226. doi:10.1016/j.compag.2017.10.018Benavente, J., Ramos-Barrado, J. ., & Heredia, A. (1998). A study of the electrical behaviour of isolated tomato cuticular membranes and cutin by impedance spectroscopy measurements. Colloids and Surfaces A: Physicochemical and Engineering Aspects, 140(1-3), 333-338. doi:10.1016/s0927-7757(97)00290-2Ando, Y., Maeda, Y., Mizutani, K., Wakatsuki, N., Hagiwara, S., & Nabetani, H. (2016). Impact of blanching and freeze-thaw pretreatment on drying rate of carrot roots in relation to changes in cell membrane function and cell wall structure. LWT - Food Science and Technology, 71, 40-46. doi:10.1016/j.lwt.2016.03.019Ando, Y., Maeda, Y., Mizutani, K., Wakatsuki, N., Hagiwara, S., & Nabetani, H. (2016). Effect of air-dehydration pretreatment before freezing on the electrical impedance characteristics and texture of carrots. Journal of Food Engineering, 169, 114-121. doi:10.1016/j.jfoodeng.2015.08.026Fuentes, A., Vázquez-Gutiérrez, J. L., Pérez-Gago, M. B., Vonasek, E., Nitin, N., & Barrett, D. M. (2014). Application of nondestructive impedance spectroscopy to determination of the effect of temperature on potato microstructure and texture. Journal of Food Engineering, 133, 16-22. doi:10.1016/j.jfoodeng.2014.02.016M’hiri, N., Veys-Renaux, D., Rocca, E., Ioannou, I., Boudhrioua, N. M., & Ghoul, M. (2016). Corrosion inhibition of carbon steel in acidic medium by orange peel extract and its main antioxidant compounds. Corrosion Science, 102, 55-62. doi:10.1016/j.corsci.2015.09.017Conesa, C., Ibáñez Civera, J., Seguí, L., Fito, P., & Laguarda-Miró, N. (2016). An Electrochemical Impedance Spectroscopy System for Monitoring Pineapple Waste Saccharification. Sensors, 16(2), 188. doi:10.3390/s16020188Conesa, C., Sánchez, L. G., Seguí, L., Fito, P., & Laguarda-Miró, N. (2017). Ethanol quantification in pineapple waste by an electrochemical impedance spectroscopy-based system and artificial neural networks. Chemometrics and Intelligent Laboratory Systems, 161, 1-7. doi:10.1016/j.chemolab.2016.12.005Ulrich, C., Petersson, H., Sundgren, H., Björefors, F., & Krantz-Rülcker, C. (2007). Simultaneous estimation of soot and diesel contamination in engine oil using electrochemical impedance spectroscopy. Sensors and Actuators B: Chemical, 127(2), 613-618. doi:10.1016/j.snb.2007.05.014Olivati, C. A., Riul, A., Balogh, D. T., Oliveira, O. N., & Ferreira, M. (2008). Detection of phenolic compounds using impedance spectroscopy measurements. Bioprocess and Biosystems Engineering, 32(1), 41-46. doi:10.1007/s00449-008-0218-4Martínez Gil, P., Laguarda-Miro, N., Camino, J. S., & Peris, R. M. (2013). Glyphosate detection with ammonium nitrate and humic acids as potential interfering substances by pulsed voltammetry technique. Talanta, 115, 702-705. doi:10.1016/j.talanta.2013.06.030Górski, Ł., Sordoń, W., Ciepiela, F., Kubiak, W. W., & Jakubowska, M. (2016). Voltammetric classification of ciders with PLS-DA. Talanta, 146, 231-236. doi:10.1016/j.talanta.2015.08.027Kumar, G., & Buchheit, R. G. (2008). Use of Artificial Neural Network Models to Predict Coated Component Life from Short-Term Electrochemical Impedance Spectroscopy Measurements. CORROSION, 64(3), 241-254. doi:10.5006/1.3278469Eddahech, A., Briat, O., Bertrand, N., Delétage, J.-Y., & Vinassa, J.-M. (2012). Behavior and state-of-health monitoring of Li-ion batteries using impedance spectroscopy and recurrent neural networks. International Journal of Electrical Power & Energy Systems, 42(1), 487-494. doi:10.1016/j.ijepes.2012.04.050Conesa, C., Seguí, L., Laguarda-Miró, N., & Fito, P. (2016). Microwaves as a pretreatment for enhancing enzymatic hydrolysis of pineapple industrial waste for bioethanol production. Food and Bioproducts Processing, 100, 203-213. doi:10.1016/j.fbp.2016.07.001Masot, R., Alcañiz, M., Fuentes, A., Schmidt, F. C., Barat, J. M., Gil, L., … Soto, J. (2010). Design of a low-cost non-destructive system for punctual measurements of salt levels in food products using impedance spectroscopy. Sensors and Actuators A: Physical, 158(2), 217-223. doi:10.1016/j.sna.2010.01.010Wold, S., Sjöström, M., & Eriksson, L. (2001). PLS-regression: a basic tool of chemometrics. Chemometrics and Intelligent Laboratory Systems, 58(2), 109-130. doi:10.1016/s0169-7439(01)00155-1Legin, Zadorozhnaya, Khaydukova, Kirsanov, Rybakin, Zagrebin, … Legin. (2019). Rapid Evaluation of Integral Quality and Safety of Surface and Waste Waters by a Multisensor System (Electronic Tongue). Sensors, 19(9), 2019. doi:10.3390/s19092019Garcia-Breijo, E., Atkinson, J., Gil-Sanchez, L., Masot, R., Ibañez, J., Garrigues, J., … Olguin, C. (2011). A comparison study of pattern recognition algorithms implemented on a microcontroller for use in an electronic tongue for monitoring drinking waters. Sensors and Actuators A: Physical, 172(2), 570-582. doi:10.1016/j.sna.2011.09.039Garcia-Breijo, E., Garrigues, J., Sanchez, L., & Laguarda-Miro, N. (2013). An Embedded Simplified Fuzzy ARTMAP Implemented on a Microcontroller for Food Classification. Sensors, 13(8), 10418-10429. doi:10.3390/s130810418Brezmes, J., Cabre, P., Rojo, S., Llobet, E., Vilanova, X., & Correig, X. (2005). Discrimination between different samples of olive oil using variable selection techniques and modified fuzzy artmap neural networks. IEEE Sensors Journal, 5(3), 463-470. doi:10.1109/jsen.2005.846186Ibáñez Civera, J., Garcia Breijo, E., Laguarda Miró, N., Gil Sánchez, L., Garrigues Baixauli, J., Romero Gil, I., … Alcañiz Fillol, M. (2011). Artificial neural network onto eight bit microcontroller for Secchi depth calculation. Sensors and Actuators B: Chemical, 156(1), 132-139. doi:10.1016/j.snb.2011.04.001Fricke, H., & Morse, S. (1925). THE ELECTRIC RESISTANCE AND CAPACITY OF BLOOD FOR FREQUENCIES BETWEEN 800 AND 4½ MILLION CYCLES. Journal of General Physiology, 9(2), 153-167. doi:10.1085/jgp.9.2.153Damez, J.-L., Clerjon, S., Abouelkaram, S., & Lepetit, J. (2007). Dielectric behavior of beef meat in the 1–1500kHz range: Simulation with the Fricke/Cole–Cole model. Meat Science, 77(4), 512-519. doi:10.1016/j.meatsci.2007.04.028Zhang, L., Shen, H., & Luo, Y. (2010). Study on the electric conduction properties of fresh and frozen-thawed grass carp (Ctenopharyngodon idellus) and tilapia(Oreochromis niloticus). International Journal of Food Science & Technology, 45(12), 2560-2564. doi:10.1111/j.1365-2621.2010.02428.

Fault detection in a three-phase inverter fed circuit: Enhancing the Tripping capability of a UPS circuit breaker using wave shape recognition algorithm

Uninterruptible power supplies (UPS) are electrical devices that protect sensitive loads from power line disturbances such as source side overcurrents caused by overvoltage and power surges. The critical load in a double conversion UPS system is supplied from an invert-er. When overcurrents occur on the load side of double conversion UPS systems, both the UPS system’s inverter and the critical load connected to it stand a high risk of damage. Load side overcurrents due to short circuits, ground faults and motor/transformer start-up are very damaging to power electronic components, electrical equipment and cable connections. There exists circuit breakers on the load side designed to trip when a huge overcurrent occurs, thereby clearing the fault. A circuit breaker is normally sized and installed based on the maxi-mum capacity of the host system and trips when a predetermined overcurrent is recorded within a specific period of time. The UPS system’s inverter has a pre-set current limit value to protect insulated-gate bipolar transistors (IGBTs) from damage. During an overcurrent, invert-ers can supply a fault current whose peak value is limited to the IGBT current limit value. This inverter supplied fault current is not high enough to trip the circuit breaker. After an extended period of overcurrent, UPS internal tripping will be activated and all loads lose power. Opera-tion of the UPS in bypass mode supplies the required fault current but exposes the sensitive load to power line distortions. Therefore, it is desired to always supply the critical load via the inverter. This study targets to design a detection algorithm for short circuits and ground faults with a detection time faster than the UPS system’s internal tripping in order to isolate the faulted ar-ea, when the inverter is supplying the critical load. To achieve this, first, a MATLAB model was designed to aid in preliminary studies of fault detection through analysing the system behaviour. Secondly, literature review was conducted and a fault detection method selected with the help of the MATLAB model. Next, laboratory tests on a real UPS system were carried out and compared to the MATLAB results. Lastly, the detection algorithm was designed, im-plemented and tested on a real double conversion UPS system. The test results indicate that the implemented detection algorithm successfully detects short circuits and ground faults well within the desired time. It also successfully distinguishes short circuits and ground faults from other sources of overcurrents such as overloading and transformer inrush current. Future development of this study includes additional features such as a fault classification method proposed for implementation to improve the UPS debugging process during maintenance. Moreover, the detection algorithm will also be refined and devel-oped further to activate a circuit that discharges a current pulse to increase the fault current fed to the circuit breaker

Investigation of high bandwith biodevices for transcutaneous wireless telemetry

PhD ThesisBIODEVICE implants for telemetry are increasingly applied today in various areas applications. There are many examples such as; telemedicine, biotelemetry, health care, treatments for chronic diseases, epilepsy and blindness, all of which are using a wireless infrastructure environment. They use microelectronics technology for diagnostics or monitoring signals such as Electroencephalography or Electromyography. Conceptually the biodevices are defined as one of these technologies combined with transcutaneous wireless implant telemetry (TWIT). A wireless inductive coupling link is a common way for transferring the RF power and data, to communicate between a reader and a battery-less implant. Demand for higher data rate for the acquisition data returned from the body is increasing, and requires an efficient modulator to achieve high transfer rate and low power consumption. In such applications, Quadrature Phase Shift Keying (QPSK) modulation has advantages over other schemes, and double the symbol rate with respect to Binary Phase Shift Keying (BPSK) over the same spectrum band. In contrast to analogue modulators for generating QPSK signals, where the circuit complexity and power dissipation are unsuitable for medical purposes, a digital approach has advantages. Eventually a simple design can be achieved by mixing the hardware and software to minimize size and power consumption for implantable telemetry applications. This work proposes a new approach to digital modulator techniques, applied to transcutaneous implantable telemetry applications; inherently increasing the data rate and simplifying the hardware design. A novel design for a QPSK VHDL modulator to convey a high data rate is demonstrated. Essentially, CPLD/FPGA technology is used to generate hardware from VHDL code, and implement the device which performs the modulation. This improves the data transmission rate between the reader and biodevice. This type of modulator provides digital synthesis and the flexibility to reconfigure and upgrade with the two most often languages used being VHDL and Verilog (IEEE Standard) being used as hardware structure description languages. The second objective of this thesis is to improve the wireless coupling power (WCP). An efficient power amplifier was developed and a new algorithm developed for auto-power control design at the reader unit, which monitors the implant device and keeps the device working within the safety regulation power limits (SAR). The proposed system design has also been modeled and simulated with MATLAB/Simulink to validate the modulator and examine the performance of the proposed modulator in relation to its specifications.Higher Education Ministry in Liby

Measurements, Models, Systems and Design

531 s.

Design of an intelligent embedded system for condition monitoring of an industrial robot

PhD ThesisIndustrial robots have long been used in production systems in order to improve productivity, quality and safety in automated manufacturing processes. There are significant implications for operator safety in the event of a robot malfunction or failure, and an unforeseen robot stoppage, due to different reasons, has the potential to cause an interruption in the entire production line, resulting in economic and production losses. Condition monitoring (CM) is a type of maintenance inspection technique by which an operational asset is monitored and the data obtained is analysed to detect signs of degradation, diagnose the causes of faults and thus reduce maintenance costs. So, the main focus of this research is to design and develop an online, intelligent CM system based on wireless embedded technology to detect and diagnose the most common faults in the transmission systems (gears and bearings) of the industrial robot joints using vibration signal analysis. To this end an old, but operational, PUMA 560 robot was utilized to synthesize a number of different transmission faults in one of the joints (3 - elbow), such as backlash between the gear pair, gear tooth and bearing faults. A two-stage condition monitoring algorithm is proposed for robot health assessment, incorporating fault detection and fault diagnosis. Signal processing techniques play a significant role in building any condition monitoring system, in order to determine fault-symptom relationships, and detect abnormalities in robot health. Fault detection stage is based on time-domain signal analysis and a statistical control chart (SCC) technique. For accurate fault diagnosis in the second stage, a novel implementation of a time-frequency signal analysis technique based on the discrete wavelet transform (DWT) is adopted. In this technique, vibration signals are decomposed into eight levels of wavelet coefficients and statistical features, such as standard deviation, kurtosis and skewness, are obtained at each level and analysed to extract the most salient feature related to faults; the artificial neural network (ANN) is then used for fault classification. A data acquisition system based on National Instruments (NI) software and hardware was initially developed for preliminary robot vibration analysis and feature extraction. The transmission faults induced in the robot can change the captured vibration spectra, and the robot’s natural frequencies were established using experimental modal analysis, and also the fundamental fault frequencies for the gear transmission and bearings were obtained and utilized for preliminary robot condition monitoring. In addition to simulation of different levels of backlash fault, gear tooth and bearing faults which have not been previously investigated in industrial robots, with several levels of ii severity, were successfully simulated and detected in the robot’s joint transmission. The vibration features extracted, which are related to the robot healthy state and different fault types, using the data acquisition system were subsequently used in building the SCC and ANN, which were trained using part of the measured data set that represents the robot operating range. Another set of data, not used within the training stage, was then utilized for validation. The results indicate the successful detection and diagnosis of faults using the key extracted parameters. A wireless embedded system based on the ZigBee communication protocol was designed for the application of the proposed CM algorithm in real-time, using an Arduino DUE as the core of the wireless sensor unit attached on the robot arm. A Texas Instruments digital signal processor (TMS320C6713 DSK board) was used as the base station of the wireless system on which the robot’s fault diagnosis algorithm is run. To implement the two stages of the proposed CM algorithm on the designed embedded system, software based on the C programming language has been developed. To demonstrate the reliability of the designed wireless CM system, experimental validations were performed, and high reliability was shown in the detection and diagnosis of several seeded faults in the robot. Optimistically, the established wireless embedded system could be envisaged for fault detection and diagnostics on any type of rotating machine, with the monitoring system realized using vibration signal analysis. Furthermore, with some modifications to the system’s hardware and software, different CM techniques such as acoustic emission (AE) analysis or motor current signature analysis (MCSA), can be applied.Iraqi government, represented by the Ministry of Higher Education and Scientific Research, the Iraqi Cultural Attaché in London, and the University of Technology in Baghda

Dynamically reconfigurable bio-inspired hardware

During the last several years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modifying their configuration bitstream, providing high architectural flexibility, while guaranteeing high performance. These configurability features have received special interest from computer architects: one can find several reconfigurable coprocessor architectures for cryptographic algorithms, image processing, automotive applications, and different general purpose functions. On the other hand we have bio-inspired hardware, a large research field taking inspiration from living beings in order to design hardware systems, which includes diverse topics: evolvable hardware, neural hardware, cellular automata, and fuzzy hardware, among others. Living beings are well known for their high adaptability to environmental changes, featuring very flexible adaptations at several levels. Bio-inspired hardware systems require such flexibility to be provided by the hardware platform on which the system is implemented. In general, bio-inspired hardware has been implemented on both custom and commercial hardware platforms. These custom platforms are specifically designed for supporting bio-inspired hardware systems, typically featuring special cellular architectures and enhanced reconfigurability capabilities; an example is their partial and dynamic reconfigurability. These aspects are very well appreciated for providing the performance and the high architectural flexibility required by bio-inspired systems. However, the availability and the very high costs of such custom devices make them only accessible to a very few research groups. Even though some commercial FPGAs provide enhanced reconfigurability features such as partial and dynamic reconfiguration, their utilization is still in its early stages and they are not well supported by FPGA vendors, thus making their use difficult to include in existing bio-inspired systems. In this thesis, I present a set of architectures, techniques, and methodologies for benefiting from the configurability advantages of current commercial FPGAs in the design of bio-inspired hardware systems. Among the presented architectures there are neural networks, spiking neuron models, fuzzy systems, cellular automata and random boolean networks. For these architectures, I propose several adaptation techniques for parametric and topological adaptation, such as hebbian learning, evolutionary and co-evolutionary algorithms, and particle swarm optimization. Finally, as case study I consider the implementation of bio-inspired hardware systems in two platforms: YaMoR (Yet another Modular Robot) and ROPES (Reconfigurable Object for Pervasive Systems); the development of both platforms having been co-supervised in the framework of this thesis

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

Robust eletronic hardware system based on quorum sensing

Abstract. Electronic systems designed by man have a high level of complexity. This feature joined with its sequential operation has enabled the susceptibility to failures. In critical applications, this problem has been traditionally attacked duplicating the entire system (redundancy), and using a central control system. The term robust, word appearing in the formulation and in the title of this research, refers to the system's ability to withstand damage (usually physical) without losing its functionality or operation. This research proposes a different design scheme inspired by a mechanism of gene expression control, mechanism which is dependent on cell density, and has been recently observed and characterized in the field of systemic biology, in medical research regarding the efficacy of antibiotics; gene expression responsible for social behaviors of independent cells (bacteria) using extracellular signals. In the biological model, the cell-cell communication is performed through the exchange of chemical molecules called auto inducers. This process, called Quorum Sensing (QS), allows bacteria to monitor their environment for the presence of other bacteria, and thus, to respond to fluctuations in the number and/or species present. The great parallelism of this kind of systems involves a great robustness, since it avoids the sequential structure and dependence on a central control system. In this research, a mathematical model of this process (QS) is proposed, and then, the use of this model to design some initial electronic applications, specifically in the area of robotics is shown. This model starts with the overall system behavior, and then, it focuses in an individual-level model. This design strategy allows, from the application criteria, to define the rules of behavior of each bacterium, which are the same throughout the community, in a similar way as occurs with cellular automata. In principle, the algorithm can be used in signal processing problems as originally formulated in the proposal, if these problems are formulated as a search problem. In this research the algorithm is implemented in some problems of navigation of robots establishing the navigation route as the search problem. The research objective is not to create hardware with evolving capacities, but to propose a scheme of hardware design that reflects a redundant structure. This means formulating a behavioral algorithm that can be implemented functionally on a hardware (microprocessors, microcontrollers, CPLDs, FPGAs, robots, etc.). For this purpose, research proposes the use of different platforms on which different levels of collective bacterial structures are evaluated, while maintaining the premise of QS local communication.Resumen. Los sistemas electrónicos diseñados por el hombre presentan un elevado nivel de complejidad. Esto unido con su característica de operación secuencial, ha permitido que en general se incremente la susceptibilidad a fallos. En aplicaciones críticas, este problema se ha atacado tradicionalmente con la duplicación de todo el sistema (redundancia), y el uso de un sistema de control central. El termino robusto, término que aparece en la formulación y en el título de ésta investigación, se refiere a la capacidad del sistema de soportar daños (en general físicos) sin perder su funcionalidad u operación. Esta investigación propone un esquema de diseño diferente inspirado en un mecanismo de control de expresiones genéticas dependiente de la densidad celular, observado y caracterizado recientemente en el campo de la biología sistémica, durante investigaciones médicas en relación con la eficacia de antibióticos. Este fenómeno es el responsable de que un conjunto de células independientes (bacterias), bajo la generación de señales extra celulares, desarrolle comportamientos sociales coordinados. En el modelo biológico, la comunicación de célula a célula se realiza a través del intercambio de moléculas químicas llamadas auto inductores. Este proceso, denominado quorum sensing (QS), permite que las bacterias supervisen su ambiente para detectar la presencia de otras bacterias, y responder así a las fluctuaciones en el número y/o especies presentes. El gran paralelismo de éste tipo de sistemas conlleva una gran robustez, dado que evita la estructura secuencial y la dependencia a un sistema de control central. Aquí se plantea un modelo matemático de éste proceso (QS), y se utiliza luego éste modelo para el diseño de algunas primeras aplicaciones electrónicas, específicamente en el área de robótica. El modelo que se propone parte del comportamiento global del sistema, y luego se enfoca a un modelo a nivel de individuo. Esta estrategia de diseño permite, a partir de los criterios de la aplicación, definir las reglas de comportamiento propias de cada bacteria, que serán las mismas de toda la comunidad, de forma similar a como ocurre con los autómatas celulares. En principio, el algoritmo puede utilizarse en problemas de procesamiento de señales como originalmente se formuló en la propuesta, si estos problemas se formulan como un problema de búsqueda. En esta investigación el algoritmo se implementa en algunos problemas de navegación de robots estableciendo la ruta de navegación como el problema de búsqueda. El objetivo de la investigación no es crear hardware con capacidad evolutiva, sino proponer un esquema de diseño de hardware que refleje una estructura redundante. Esto significa formular un algoritmo de comportamiento que pueda ser implementado funcionalmente sobre un hardware (microprocesadores, microcontroladores, CPLDs, FPGAs, robots, etc.). Para ello, la investigación propone el uso de diferentes plataformas sobre las cuales se evalúan diferentes niveles de estructuras bacteriales colectivas, manteniendo siempre la premisa de comunicación local del QS.Doctorad

Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.

Esta tesis doctoral está enmarcada en el campo de investigación de la computación reconfigurable. Este campo ha experimentado un crecimiento abrumador en los últimos años como resultado de la evolución de los dispositivos reconfigurables, donde las Field Programmable Gate Arrays (FPGAs) son el máximo exponente desde el punto de vista comercial. De forma tradicional las empresas de electrónica han seleccionado las FPGAs como prototipos iníciales de productos de altas prestaciones. Luego el sistema final es integrado en Application Specific Integrated Circuits (ASICs) que se producen en grandes volúmenes perimiendo amortiza su alto coste de diseño y producción y aprovechando la ventaja del bajo coste por unidad. Por otro lado, los DSPs (Digital Signal Processing) y los microprocesadores han sido preferidos por su bajo coste ante las FPGAs el campo de los dispositivos con menores requisitos de cómputo. En los últimos años, este panorama está sufriendo una serie de cambios. Ahora el mercado busca mas soluciones “reconfigurables” ya que permiten reducir el tiempo de salida del producto al mercado (time-to-market), aumentar el tiempo del producto en el mercado (time-in-market) y además cubren los amplios requisitos de cómputo. El cambio que se observa, se debe a que los dispositivos programables han evolucionado de simples estructuras programables a complejas plataformas reconfigurables. Las FPGAs del estado de la técnica han alcanzado un grado de integración muy alto y además ahora contienen, dentro de su arquitectura programable, microprocesadores y lógica específica de procesamiento digital de señal. Otro factor sumamente importante para el cambio es que las FPGAs permiten el diseño de dispositivos cuyo hardware pueden ser adaptado, o actualizado, una vez que el producto ya esta entregado e instalado, obteniendo así una flexibilidad en el hardware comparable con la del software, donde la actualización postventa de los sistemas es una práctica muy explotada de cara a la reducción de costes y la salida rápida al mercado. Por otro lado, y sobre todo en el ámbito académico, existen dispositivos reconfigurables con distinta granularidad que permites alcanzar altas prestaciones en comparación con las FPGAs comerciales de grano fino (comparable con la de los ASICs), pero están restringidas a una aplicación o grupo de aplicaciones. A pesar de que los dispositivos reconfigurables propietarios ofrecen muchas ventajas, esta opción ha sido descartada en la presente tesis debido a que, desde el punto de vista industrial requieren, aparte del diseño del ASIC reconfigurable, el desarrollo de un entorno de diseño completo. Todo esto conlleva a un elevado coste de recursos, además del alejamiento de las propuestas de la industria. La presente tesis se ha centrado en proporcionar soluciones para dispositivos comerciales, FPGAs de grano fino, con la finalidad de aprovechar las herramientas existentes y mantener las soluciones propuestas lo más cerca posible de la industria. Los dispositivos reconfigurables proporcionan diversos métodos de reconfiguración, siendo el más atractivo la reconfiguración parcial y dinámica, ya que permite adaptar el dispositivo sin interrumpir su funcionamiento y crear dispositivos auto-adaptables. Este tipo de reconfiguración será el objeto de estudio de la tesis doctoral. La reconfiguración parcial permite tener una serie de tareas hardware (módulos que se ubican en la estructura reconfigurable) ejecutándose paralelamente en la FPGA y sustituir un bloque por otro, dependiendo de las necesidades del sistema, sin alterar el funcionamiento del resto de bloques. Esta idea básica en teoría brinda la flexibilidad del software al hardware, que combinado con su paralelismo implícito hace del sistema reconfigurable una potente herramienta que puede dar pie a la creación de sistemas adaptables o incluso autoadaptativos, supercomputadores reconfigurables y hardware bio-inspirado entre otros. Por otro lado, a pesar que algunos proveedores de FPGAs permiten la reconfiguración parcial, el uso de esta técnica aún está restringido al ámbito académico y a sistemas muy básicos. El trabajo de investigación descrito dentro de la presente tesis doctoral ha tenido por objeto el estudio de diversos aspectos de los sistemas parcialmente reconfigurables, la identificación de las principales deficiencias de las soluciones existentes y la propuesta de nuevas soluciones originales. Como resultado del estudio del estado del arte se ha visto que las soluciones existentes son poco flexibles y la escalabilidad de los sistemas que se pueden diseñar es reducida. Por ello las propuestas originales de esta tesis tienen como objetivo permitir el diseño e implementación de sistemas parcialmente reconfigurables con alta escalabilidad y flexibilidad. La tesis principal del trabajo de investigación ha sido basada en la idea que para obtener una mayor flexibilidad de los sistemas se debe desligar el diseño del sistema reconfigurable del diseño de los cores que serán consumidos por dicho sistema. La tesis doctoral ha contribuido proponiendo mejores soluciones a nivel de arquitectura, flujos de diseño y herramientas que han permitido el diseño e implementación de diversos sistemas parcialmente reconfigurables con distinto grado de flexibilidad y escalabilidad. La flexibilidad y la escalabilidad son términos que en los sistemas reconfigurables se pueden asociar a diversos aspectos. Dentro de esta tesis la flexibilidad está asociada principalmente a la diversidad de cores o tareas hardware que pueden ser consumidos o integrados en un sistema ya definido, mientras que la escalabilidad está referida al número de cores que pueden coexistir en el sistema y ser reconfigurados independientemente. Para poder diseñar sistemas flexibles y escalables, estas características deben estar cubiertas en distintos niveles. Más en detalle dentro de la presente tesis, desde el punto de vista de la arquitectura, la flexibilidad está cubierta por la posibilidad de posicionar libremente cores en una arquitectura escalable predefinida. Desde el punto de vista del sistema, la flexibilidad está reflejada por la posibilidad de no sólo de modificar o reconfigurar un core del sistema hardware, sino también de modificar las comunicaciones internas del mismo. Desde el punto de vista del dispositivo, la flexibilidad está garantizada por la transparencia en el proceso de reconfiguración. Por último, la flexibilidad en el proceso de diseño está cubierta por la definición de herramientas y flujos de diseño que permiten por un lado desligar el diseño del sistema reconfigurable del diseño de los cores para el sistema, y por otro lado que diseñadores sin conocimientos detallados de reconfiguración parcial puedan diseñar cores. Dentro de la tesis doctoral se presentan cuatro dispositivos reconfigurable integrados en distintos entornos y con distinto grado de flexibilidad que corresponde al grado de aprovechamiento de las aportaciones originales de la tesis. Las principales aportaciones de la tesis doctoral, relacionadas a cada uno de los aspectos mencionados en el párrafo anterior, y tratados en distintas partes de la tesis se resumen a continuación destacando en la medida de lo posible las diferencias con respecto al estado del arte: Se ha definido una metodología de diseño de Arquitecturas Virtuales (abstracción de la arquitectura física de la FPGA que incluye la distribución de los recursos programables en slots y la forma de interconexión de los slots). La metodología, propuesta originalmente en esta tesis, permite el diseño de sistemas reconfigurables con alta flexibilidad y escalabilidad comparadas con el estado del arte. Una solución a la adaptación de las comunicaciones internas en los sistemas reconfigurables llamada DRNoC (Dynamic Reconfigurable NoC). La solución original abarca diversos aspectos e incluye la definición de una arquitectura de interconexión para los sistemas reconfigurables basada en redes en chip (Network on Chip - NoC), la definición de métodos de reconfiguración y el direccionamiento interno del sistema, y de forma más específica para las comunicaciones basadas en redes, la definición de un formato de tramas y la arquitectura de los enrutadores. La principal diferencia de la solución propuesta con el estado del arte es que DRNoC no restringe la comunicación únicamente a NoCs y permite la definición de cualquier tipo de esquema de comunicación (NoC, punto a punto, punto a multipunto, bus, o una combinación de las anteriores) y además, permite que varios esquemas de comunicación coexistan en el mismo sistema y que funcionen de forma independiente. De esta forma la solución propuesta brinda una mayor flexibilidad que las ya existentes. Se ha propuesto una solución para la manipulación de los ficheros de configuración para las FPGA del tipo Virtex II/Pro que es la más completa comparada con el estado del arte. Asimismo, una serie de herramientas que permiten la generación y extracción de cores para sistemas reconfigurables basados en FPGA Virtex II que ha sido la primera solución existente para estas FPGA. Un flujo de diseño para cores basado en plantillas que permite el diseño de cores hardware sin ser un experto en reconfiguración parcial y sin conocer los detalles del sistema final en el que se implementará el core. El diseño, implementación y prueba de un sistema parcialmente reconfigurable basado en FPGAs comerciales de grano fino para redes de sensores. La primera aproximación existente en el estado del arte al uso de los sistemas parcialmente reconfigurables en las redes de sensores. La integración de un sistema reconfigurable en un entorno cliente-servidor que incluye un original sistema de control de la reconfiguración. Una solución para la depuración de los sistemas reconfigurables. Un sistema de emulación y prototipado rápido de las comunicaciones dentro de un chip basado originalmente en la idea de la reutilización de cores hardware por medio de la técnica de reconfiguración parcial. Como conclusión global del trabajo de investigación realizado cabe destacar que la presente tesis ha dado lugar a la creación y consolidación de una línea de investigación en el grupo de electrónica digital del Centro de Electrónica Industrial que actualmente se encuentra entre las más activas y de mayor importancia. Además, el trabajo de investigación y la divulgación de las aportaciones originales han permitido que el centro de investigación pase a formar parte del estado del arte de los sistemas parcialmente reconfigurables. The thesis is enclosed in the research area of reconfigurable computing which, in the last years, has experienced a remarkable growth as a result of the impressive evolution of reconfigurable devices. In this area, Field Programmable Gate Arrays (FPGAs) are the most outstanding representative from the commercial point of view. Traditionally FPGAs have been used for prototyping, in previous to the final Application Specific Integrated Circuit (ASIC) design stages. However, the interest in the integration of FPGAs in final products has been growing in the last years. FPGAs are preferred for small production volumes, where the ASIC masks high cost is unaffordable and also in products where time-to-market is a priority, and waiting for a complete ASIC design cycle is not desirable. State of the art FPGAs are highly integrated electronic circuits, composed of tens of millions of system gates, with competitive speed, performance and configurability. These devices have evolved from simple gate arrays to complex platforms that include embedded memory, multipliers and even microprocessors and digital signal processing elements. Additionally, the fine grain nature of the reconfigurable arrays, make FPGAs suitable for a broad set of application domains. On the other side, and mostly in the academic community, there are custom reconfigurable devices with different granularity levels that permit to achieve higher performance, compared to commercial FPGAs, but for a certain application domain. Although there are very good solutions in the academic state of the art, their main drawback from the industry point of view is that they require specific design environments and also, that the efforts and resources needed for designing such solutions are very high. This thesis work is focused on providing solutions that target commercial fine grain reconfigurable devices, FPGAs, in order to take advantage of existing tools and to keep the proposed solutions closer to the industry. Today FPGAs provide different reconfiguration options. Among them, the most challenging one is partial reconfiguration. This feature has special interest, as it permits system updates on the fly once the device is deployed, without the need of stopping it and without theoretical loss of performance. Partial reconfiguration is also an attractive feature because it permits to allocate different tasks/cores running in parallel in the device and change them on the fly as needed without disturbing other tasks/cores. This basic idea, brings software-like flexibility to hardware which, in combination with its inherited parallelism, opens the door for a broad amount of possibilities and applications, like runtime adaptive super-computing, adaptive embedded software ii accelerators, bio-inspired, self-reconfigurable and self-arrangeable systems. However, even though some commercial FPGAs provide partial reconfiguration features, its utilization is still in its early stages and it is not well supported by FPGA vendors, making its exploitation in real electronic systems very difficult. Therefore, there are several academic groups working to provide alternative solutions for the design and implementation of partially reconfigurable systems based on commercial FPGAs that intend to stimulate their integration and use in the industry. This research work intents to study different aspects of partially reconfigurable system on-chip and contribute with flexibility improvements. The main idea that will be followed along the thesis is that the design of reconfigurable systems will be considered an independent process from the design of cores that will be consumed by the system. This approach involves the design of flexible and scalable partial runtime reconfigurable systems, where most of the thesis contribution will be focused. More in detail, this thesis will contribute to improve architecture solutions, design tools and design flows of partially reconfigurable systems for commercial FPGAs and provide systems with higher flexibility and scalability. Flexibility and scalability in a reconfigurable system are terms that can be related to several aspects. In this thesis flexibility is mainly related to the diversity of tasks or cores a system can consume, while scalability is connected to the number of cores that can run in parallel and be independently reconfigured. Flexibility and scalability have to be covered by the system at different levels and the work presented in this thesis will contribute in all the specific levels. More in detail, from an architectural point of view, flexibility is reflected by the possibility of freely loading tasks or cores in a defined, scalable architecture. From the system point of view, flexibility is related to the possibility of modifying not only the system functionality by loading different tasks, but also to adapt the on-chip communications. From the device point of view, flexibility is reflected by the reconfiguration process transparency and, from the design point of view, it is oriented to the definition of design tools and flows that will permit, as far as possible, non specialized designers to design cores for a partially reconfigurable system and without knowing the system details. All the original proposed solutions, in each individual aspect, will be compared with the state of the art and complete systems solutions will be designed and will be integrated in different application domains in order to validate the thesis proposals. In order to achieve better understanding of the thesis and to facilitate the comparison with some, selected, related work, the thesis structure is not traditional. Instead of including a state of the art and a result Chapter, each Chapter is focused on a specific aspect of partially reconfigurable system design and includes state of the art and result sections. The first chapter, Chapter 1, introduces the main concepts to be used in the thesis. Chapter 2 is focused on reconfigurable systems architectures, contributing with architecture solutions and a design method. Chapter 3 proposes a solution that enhances the features of the architectures defined in Chapter 2, and provides more flexibility to the entire system by extending reconfiguration to the on-chip communication. Chapter 4 is related to the design flows and tools, where contributions are made in both aspects and the proposed solutions are compared with the state of the Abstract and Thesis Organization iii art. Complete systems, with different independency levels, are presented in Chapter 5 in order to validate the thesis contributions. Conclusions, a summary of contributions and the future work are included in Chapter 6. A more detailed description of each Chapter content is presented below: Chapter 1 provides an introduction to the reconfigurable systems based on FPGAs topic, by first defining the place of FPGAs in the electronic industry and afterwards, introducing the main concepts to be used along the thesis. Although the focus is put on commercial reconfigurable devices, some custom reconfigurable systems are also described in order to have a complete view of the options in reconfigurable devices. The Chapter discuses the thesis main topic, related to partial runtime reconfigurable systems, highlighting its main advantages and disadvantages and, introducing some of the approaches to be followed in this thesis. The main term introduced in this Chapter, associated to reconfigurable systems architectures, is ”Virtual Architecture”. The term defines the architecture of the partially reconfigurable system and how the different regions it is composed of are interconnected. A brief summary of the thesis main goals is included at the end of the Chapter. The main topic of Chapter 2 is related to reconfigurable systems architectures design. The Chapter includes a specific state of the art section that reviews some existing architecture solutions. After that, a general method for virtual architectures design, an original thesis contribution, is presented in detail. Afterwards, the method is applied to the design of general one dimensional (1D) and two dimensional (2D) architectures for Xilinx Virtex II/Pro FPGAs and, as an example, following the specific steps of the method, two 1D, bus based, architectures are designed. The architecture buses are compared with two state of the art solutions in terms of area and performance in the results section of the same Chapter. Chapter 3 is focused on reconfigurable systems on-chip communication issues, where the need of adaptability is the main topic. Again, a state of the art description of some 2D reconfigurable systems is presented at the beginning of the Chapter and, afterwards, an original solution, called Dynamic Reconfigurable NoC (DRNoC), is proposed. This solution covers different aspects. First, an architecture oriented to support adaptability in the on-chip communications is originally proposed. The architecture is mapped to a Virtex II FPGA by modifying a virtual architecture from the general ones presented in Chapter 2. Second, two types of reconfigurations that span through different levels of the OSI communication model are originally proposed. Third, a set of Network on Chip models, focused on the communication adaptability are designed and/or adapted and presented in the Chapter, along with an original NoC packet format and router architecture. These models are mapped to the DRNoC architecture and implementation cost parameters are defined and used to evaluate different implementation options. Regarding the architecture reconfigurability, it is important to remark that along the entire Chapter, intermediate test of possible partial reconfigurations and test results are included. At the end of the Chapter, the proposed architecture is compared with the state of the art using a set of structural parameters taken from a reference work and complemented with others defined in the Chapter. Chapter 4, focuses on the design tools and flows for partially reconfigurable systems. Again, an overview of the state of the art is included at the beginning of the Chapter. Abstract and Thesis Organization iv Afterwards, an original software solution for Virtex II configuration files (bitstreams) manipulations is presented. The first part of the solution is a study of the Virtex II/Pro FPGA bitstream format, used to define a set of equations for accessing a specific bitstream resource (at register or block level). Based on these equations, a set of tools for bitstream manipulation that target resource restricted devices are originally presented. Also, a design flow, based on systems and virtual architectures templates, which permits a straightforward core design by non partial reconfiguration experts and without knowing the system details, is originally proposed. In Chapter 5 four reconfigurable systems with different flexibility level, which corresponds to the level of the thesis proposals exploitation, are presented. The selected application domains attempt to demonstrate different advantages of the use of partial runtime reconfigurable systems and therefore are mainly a proof of concept. The first domain belongs to the wireless sensor networks, where t