Electrical Optimization of a Plug-In Hybrid Electric Vehicle

Hybrid electric vehicles electrification and optimization is a prominent part of today’s automotive industry. GM and the Department of Energy challenge 16 universities across North America to redesign a Chevrolet Camaro into a hybrid electric vehicle. This thesis will address how Embry Riddle Aeronautical University’s EcoCAR team electrified and optimized the vehicle. The objective of the thesis is to optimize the electric portion of the vehicle, particularly the low voltage circuitry. Prior work is discussed in detail on the vehicle communication bus, building the power distribution unit and the approach the electrical team took when building the electric portion of the vehicle. Simulations were done based on manufacturer data and bench tests to create an ideal model. Data was collected from the vehicle and compared to the ideal model to determine errors in the electrical system. An emphasis was placed on critical and high power components to simplify the simulation model. The issues found were alleviated by conducting research, using research analysis, physically changing the system or by implementing control strategies. Most of the issues came from the power distribution unit and implementation techniques such as grounding. The MOSFETs within the power distribution unit was not fully turning on and off, and which was due to a slow RC time constant occurring on the gate of the transistors. By replacing the resistors, this issue was mitigated. Every problem found was properly mitigated to an acceptable industry or research standard

Power Converters and Power Quality

This paper discusses the subject of power quality for power converters. The first part gives an overview of most of the common disturbances and power quality issues in electrical networks for particle accelerators, and explains their consequences for accelerator operation. The propagation of asymmetrical network disturbances into a network is analysed. Quantitative parameters for network disturbances in a typical network are presented, and immunity levels for users' electrical equipment are proposed. The second part of this paper discusses the technologies and strategies used in particle accelerator networks for power quality improvement. Particular focus is given to networks supplying loads with cycling active and reactive power.Comment: 26 pages, contribution to the 2014 CAS - CERN Accelerator School: Power Converters, Baden, Switzerland, 7-14 May 201

Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology

Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning applications has increased the demand of MEMS-based digital microphones. Mobile devices have several microphones enabling noise canceling, acoustic beamforming and speech recognition. With the development of machine learning applications the interest to integrate sensors with neural networks has increased. This has driven the interest to develop digital microphones in nanometer CMOS nodes where the microphone analog-front end and digital processing, potentially including neural networks, is integrated on the same chip. Traditionally, analog-to-digital converters (ADCs) in digital microphones have been implemented using high order Sigma-Delta modulators. The most common technique to implement these high order Sigma-Selta modulators is switchedcapacitor CMOS circuits. Recently, to reduce power consumption and make them more suitable for tasks that require always-on operation, such as keyword recognition, switched-capacitor circuits have been improved using inverter-based operational amplifier integrators. Alternatively, switched-capacitor based Sigma- Delta modulators have been replaced by continuous time Sigma-Delta converters. Nevertheless, in both implementations the input signal is voltage encoded across the modulator, making the integration in smaller CMOS nodes more challenging due to the reduced voltage supply. An alternative technique consists on encoding the input signal on time (or frequency) instead of voltage. This is what time-encoded converters do. Lately, time-encoding converters have gained popularity as they are more suitable to nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs). VCO-ADCs can be implemented using CMOS inverter based ring oscillators (RO) and digital circuitry. They also show noise-shaping properties. This makes them a very interesting alternative for implementation of ADCs in nanometer CMOS nodes. Nevertheless, two main circuit impairments are present in VCO-ADCs, and both come from the oscillator non-idealities. The first of them is the oscillator phase noise, that reduces the resolution of the ADC. The second is the non-linear tuning curve of the oscillator, that results in harmonic distortion at medium to high input amplitudes. In this thesis we analyze the use of time encoding ADCs for MEMS microphones with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations for the noise transfer function (NTF) of a third order sigma-delta using a second order filter and the NSQ are presented. Secondly, we move our attention to the topic of RO-ADCs. We present a high dynamic range MEMS microphone 130nm CMOS chip based on an open-loop VCO-ADC. This dissertation shows the implementation of the analog front-end that includes the oscillator and the MEMS interface, with a focus on achieving low power consumption with low noise and a high dynamic range. The digital circuitry is left to be explained by the coauthor of the chip in his dissertation. The chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5% at 128 dBSPL with a power consumption of 438μW. After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement an unsampled feedback loop around the oscillator. The objective is to reduce distortion. Additionally phase noise mitigation is achieved. A first topology including an operational amplifier to increase the loop gain is analyzed. The design is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR with an analog power consumption of 600μW. A second topology without the operational amplifier is also analyzed. Two chips are designed with this topology. The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto- digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a power consumption of 482μW. The second chip includes only the oscillator and is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog power consumption is 153μW. To finish this thesis, two circuits that use an FDR with a ring oscillator are presented. The first is a capacity-to-digital converter (CDC). The second is a filter made with an FDR and an oscillator intended for voice activity detection tasks (VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de machine-learning han aumentado la demanda de micrófonos digitales basados en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación de ruido, el beamforming o conformación de haces y el reconocimiento de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde el front-end analógico y el procesamiento digital del micrófono, que puede incluir redes neuronales, está integrado en el mismo chip. Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos digitales han sido implementados utilizando moduladores Sigma-Delta de orden elevado. La técnica más común para implementar estos moduladores Sigma- Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente, para reducir el consumo de potencia y hacerlos más adecuados para las tareas que requieren una operación continua, como el reconocimiento de palabras clave, los convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con el uso de integradores implementados con amplificadores operacionales basados en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas han sido reemplazados por moduladores en tiempo continuo. No obstante, en ambas implementaciones, la señal de entrada es codificada en voltaje durante el proceso de conversión, lo que hace que la integración en nodos CMOS más pequeños sea complicada debido a la menor tensión de alimentación. Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación temporal. Recientemente, los convertidores de codificación temporal han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos que los convertidores Sigma-Delta. Entre los que más interés han despertado encontramos los ADCs basados en osciladores controlados por tensión (VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo (RO) implementados con inversores CMOS y circuitos digitales. Esta familia de convertidores también tiene conformado de ruido. Esto los convierte en una alternativa muy interesante para la implementación de convertidores en nodos CMOS nanométricos. Sin embargo, dos problemas principales están presentes en este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no lineal del oscilador, lo que causa distorsión a amplitudes medias y altas. En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos MEMS, con especial interés en ADCS basados en osciladores de anillo (RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador agrega un orden adicional de conformado de ruido al modulador, mejorando la resolución. En este documento se explica el cuantificador y obtienen las ecuaciones para la función de transferencia de ruido (NTF) de un sigma-delta de tercer orden usando un filtro de segundo orden y el NSQ. En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos el chip de un micrófono MEMS de alto rango dinámico en CMOS de 130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación del front-end analógico que incluye el oscilador y la interfaz con el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La descripción del back-end digital se deja para la tesis del couator del chip. La SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD de 1,5% a 128 dBSPL y un consumo de potencia de 438μW. Finalmente, se analiza el uso de una resistencia dependiente de frecuencia (FDR) para implementar un bucle de realimentación no muestreado alrededor del oscilador. El objetivo es reducir la distorsión. Además, también se logra la mitigación del ruido de fase del oscilador. Se analyza una primera topologia de realimentación incluyendo un amplificador operacional para incrementar la ganancia de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador operacional. Se fabrican y miden dos chips diseñados con esta topologia. El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de 76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el el consumo de potencia analógica es de 153μW. Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador en anillo. El primero es un convertidor de capacidad a digital (CDC). El segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout

Rectifier power converter for marine applications with compensating capacitor and boost converter stage

Environmental concerns and new emissions regulations, as well as increasing power needs for marine electrical grids, are pushing the development of more efficient power converters for shipboard power systems (SPS). The priorities for SPS design are reliability and power density especially in harsh operating conditions. Safety, space, and weight are of paramount importance requirements on a ship. One factor affecting the design of SPS is the high inductive impedance presented by ac generators, which requires high voltage ratios to compensate for. Therefore, ac-dc converters, sitting as they do between ac generators and the dc bus of the SPS, are identified as a point of potential development to improve the form factor and efficiency of SPS. A novel series capacitor compensation technique is proposed and applied to an ac-dc boost rectifier. Time-averaged equations are derived and compared to simulated waveforms generated using MATLAB/Simulink. Total harmonic distortion (THD) and power factor (PF) are calculated and measured. THD is found to be the limiting factor in designing the proposed compensator. The circuit is simulated in one and three phases, and several input-to-output voltage ratios are compared. To verify the practicality of the compensation method, a single-phase 1 kW rated prototype is implemented and practical results are presented and compared with the simulated waveforms. It is found that the compensation method can control THD to acceptable levels for a large range of inductive impedances, suggesting that this solution should be further developed and investigated for application in SPS.Environmental concerns and new emissions regulations, as well as increasing power needs for marine electrical grids, are pushing the development of more efficient power converters for shipboard power systems (SPS). The priorities for SPS design are reliability and power density especially in harsh operating conditions. Safety, space, and weight are of paramount importance requirements on a ship. One factor affecting the design of SPS is the high inductive impedance presented by ac generators, which requires high voltage ratios to compensate for. Therefore, ac-dc converters, sitting as they do between ac generators and the dc bus of the SPS, are identified as a point of potential development to improve the form factor and efficiency of SPS. A novel series capacitor compensation technique is proposed and applied to an ac-dc boost rectifier. Time-averaged equations are derived and compared to simulated waveforms generated using MATLAB/Simulink. Total harmonic distortion (THD) and power factor (PF) are calculated and measured. THD is found to be the limiting factor in designing the proposed compensator. The circuit is simulated in one and three phases, and several input-to-output voltage ratios are compared. To verify the practicality of the compensation method, a single-phase 1 kW rated prototype is implemented and practical results are presented and compared with the simulated waveforms. It is found that the compensation method can control THD to acceptable levels for a large range of inductive impedances, suggesting that this solution should be further developed and investigated for application in SPS

Implementation of a Distribution Static Compensator D-STATCOM: Hardware and Firmware Description

This paper describes the implementation of a distribution static power compensator (D-STATCOM) for reactive compensation in electric distribution networks. A three-phase inverter of six pulses with two levels was developed. Hardware implementation of different stages (sensors, power switching, passive elements, and processor) is fully described. Firmware that allows D-STATCOM operation was implemented on a TMS3202F DSP (Texas Instruments) using a modular approach. Correct operation of the D-STATCOM prototype is verified with experimental results