Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort, enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40-nm testchip, graceful degradation of 0.3bit/100mV is achieved when V_DD is over-scaled down to 0.8V, and 1.4bit/100mV when further scaled down to 0.6V. The proposed DAC enables dynamic power-resolution tradeoff with 3X (2X) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40nm consumes 55µW at 27kS/s (9.1µW at 13.5kS/s) at a compact area of 500µm^2 and low voltage of 0.55V

Analog processing by digital gates: fully synthesizable IC design for IoT interfaces

Analog integrated circuits do not take advantage of scaling and are easily the bottleneck in terms of cost and performance in Internet of Things (IoT) sensor nodes integrated in nanoscale technologies. While this challenge is most commonly addressed by devising more “digital friendly” analog cells based on traditional design concepts, the possibility to translate analog functions into digital, so that to implement them by true digital gates, is now emerging as a promising alternative. This last approach, which challenges the idea that “analog circuits will be always needed”, is presented in this tutorial starting from the theoretical background to its application in digital-based operational amplifiers, voltage references, oscillators and data converters integrated on silicon which have proposed in recent literature. The applicability of the concepts to the design of ICs which are natively portable across technology nodes and highly reconfigurable, thus enabling dynamic energy quality scaling, as well as a low design effort and a fast time-to-market will be described

Temperature Characterization of a Fully-synthesizable Rail-to-Rail Dynamic Voltage Comparator operating down to 0.15-V

This paper deals with the performance/temperature tradeoff in an ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator made solely by digital standard cells. The digital nature of the comparator makes its design technology portable also enabling its operation at very low supply voltages down to deep sub-threshold. In particular, as sub-threshold circuits have a significant temperature dependence, this paper focuses on the comparator performance under different supply voltages and temperatures.Measurements performed on a 180nm testchip show correct operation under rail-to-rail common-mode input at a supply voltage ranging from 0.6V down to 0.15V. Moreover, the measurements under temperature variations of offset, clock-to-output delay, and power in the range from -25 °C to 75 °C show the respective performance trade-offs

Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000um^2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications. (PDF) Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS. Available from: https://www.researchgate.net/publication/336552301_Design_of_Relaxation_Digital-to-Analog_Converters_for_Internet_of_Things_Applications_in_40nm_CMOS [accessed Nov 16 2019]

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

breaking the boundaries between analogue and digital

Subject Editor Paolo Crovetti spotlight on future information processin

Emerging Relaxation and DDPM D/A Converters: Overview and Perspectives

In this paper, two emerging, digital-intensive, matching-indifferent, bitstream digital-to-analog (D/A) conversion techniques proposed in the last years, namely: the Relaxation D/A Conversion (ReDAC) and the Dyadic Digital Pulse Modulation (DDPM)-based D/A conversion, are reviewed and compared. After the basic concepts are introduced, the main challenges and research achievements over the last years are summarized and the performance of different integrated circuit (IC), field-programmable gate array (FPGA) and microcontroller-based ReDACs and DDPM-DACs are discussed and compared, highlighting advantages and open research questions. Present applications of the two techniques in voltage and current mode A/D conversion, RF modulation, digitally controlled switching-mode power converters, and machine learning accelerators will be discussed, and future application perspectives will be outlined

Software-Defined DDPM Modulators for D/A Conversion by General-Purpose Microcontrollers

The software implementation of Dyadic Digital Pulse Modulators (DDPMs) for Digital to Analog (D/A) conversion is addressed in this paper. In particular, an enhanced software DDPM implementation is proposed and compared with a plain, iterative software transposition of the basic DDPM hardware architecture. Experimental results on an 8-bit software-defined DDPM D/A converter implemented on a Texas Instrument c2000 microcontroller platform validate the approach, revealing for the novel optimized software DDPM a 6X maximum sample rate compared to the simple iterative implementation on the same microcontroller and at the same system clock frequency. Based on measurements, an 8-bit DDPM DAC featuring the proposed optimized implementation operates at 7.8kS/s with a maximum INL of 1.64LSB, a maximum DNL of 1.79LSB, an SFDR of 47.02dB and a SNDR of 45.27dB, corresponding to 7.23 ENOB, demonstrating the effectiveness and the applicability of the proposed approach to implement a low cost, software-defined D/A converters in microcontroller-based embedded systems

Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS

In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4–239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming $50.8\mu \text{W}$ , the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, $45\mu \text{W}$ power, at only $530\mu \text{m}^{2}$ area

Relaxation Digital-to-Analog Converter with Foreground Digital Self-Calibration

3noA reference-free, fully digital foreground self-calibration strategy intended to automatically tune the clock frequency of Relaxation Digital to Analog Converters (ReDACs), as demanded for linear operation, is presented in this paper. The effectiveness of the proposed approach is demonstrated by computer simulations on a 10-bit, 2MS/s ReDAC designed in 40nm CMOS and operated from a 600mV power supply voltage. After the proposed calibration, the ReDAC is shown to operate near the optimal clock frequency achieving 0.98 LSB maximum INL, 1.00 LSB maximum DNL and 9.06 ENOB.partially_openopenPaolo Crovetti; Roberto Rubino; Francesco MusolinoCrovetti, PAOLO STEFANO; Rubino, Roberto; Musolino, Francesc