Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

2 GHz +14 dBm CMOS power amplifier for Low Power Wide Area Networks

Abstract. The design of a radiofrequency power amplifier (RF PA) for narrowband low-power wide area networks is presented in this thesis. Particularly, this RF PA is compliant with the 3GPP TS 36.101 standard for a NB1 device within the Power Class 6. To minimize silicon area consumption, this CMOS RF PA employs a single-ended single-stage topology, avoiding inter-stage matching network inductors and output baluns. This RF PA produces +14 dBm of output power with a PAE of 25% and an EVM better than 4% (−28 dB). Also, its out-of-band and spurious emissions satisfy the standard specifications with a large margin. Furthermore, it provides high ruggedness, tolerating an antenna mismatch with a VSWR of 8:1

Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements