A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (s) are the highest when compared to other reported FCOTAs in the literature

Low-Voltage Bulk-Driven Amplifier Design and Its Application in Implantable Biomedical Sensors

The powering unit usually represents a significant component of the implantable biomedical sensor system since the integrated circuits (ICs) inside for monitoring different physiological functions consume a great amount of power. One method to reduce the volume of the powering unit is to minimize the power supply voltage of the entire system. On the other hand, with the development of the deep sub-micron CMOS technologies, the minimum channel length for a single transistor has been scaled down aggressively which facilitates the reduction of the chip area as well. Unfortunately, as an inevitable part of analytic systems, analog circuits such as the potentiostat are not amenable to either low-voltage operations or short channel transistor scheme. To date, several proposed low-voltage design techniques have not been adopted by mainstream analog circuits for reasons such as insufficient transconductance, limited dynamic range, etc. Operational amplifiers (OpAmps) are the most fundamental circuit blocks among all analog circuits. They are also employed extensively inside the implantable biosensor systems. This work first aims to develop a general purpose high performance low-voltage low-power OpAmp. The proposed OpAmp adopts the bulk-driven low-voltage design technique. An innovative low-voltage bulk-driven amplifier with enhanced effective transconductance is developed in an n-well digital CMOS process operating under 1-V power supply. The proposed circuit employs auxiliary bulk-driven input differential pairs to achieve the input transconductance comparable with the traditional gate-driven amplifiers, without consuming a large amount of current. The prototype measurement results show significant improvements in the open loop gain (AO) and the unity-gain bandwidth (UGBW) compared to other works. A 1-V potentiostat circuit for an implantable electrochemical sensor is then proposed by employing this bulk-driven amplifier. To the best of the author’s knowledge, this circuit represents the first reported low-voltage potentiostat system. This 1-V potentiostat possesses high linearity which is comparable or even better than the conventional potentiostat designs thanks to this transconductance enhanced bulk-driven amplifier. The current consumption of the overall potentiostat is maintained around 22 microampere. The area for the core layout of the integrated circuit chip is 0.13 mm2 for a 0.35 micrometer process

Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step

Design and characterization of low voltage operational amplifiers for smart sensors using low cost CMOS technology

This bachelor thesis brackets the use of different OTA topologies and compares them under the scope of their application as low power comparators and adders for a ΣΔ ADC. This was undertaken under the “Design and characterization of main building blocks for Medical instrumentation ADCs” research project and, more specifically, in the “Design of a Low-IF Sigma-Delta Modulator” section. The researched topologies include a folded cascode, telescopic cascode, class A Miller as well as a class AB Miller. The implementation was performed at transistor level of the for all topologies in a 0.18 μm with original 1.8 V, downscaled to 1.5 V with the goal of reducing power consumption.Ingeniería Biomédic

An Ultra-Low-Power Track-and-Hold Amplifier

The future of electronics is the Internet of Things (IoT) paradigm, where always-on devices and sensors monitor and transform everyday life. A plethora of applications (such as navigating drivers past road hazards or monitoring bridge and building stresses) employ this technology. These unattended ground-sensor applications require decade(s)-long operational life-times without battery changes. Such electronics demand stringent performance specifications with only nano-Watt power levels.This thesis presents an ultra-low-power track-and-hold amplifier for such systems. It serves as the front-end of a SAR-ADC or the building block for equalizers or filters. This amplifier\u27s design attains exceptional hold times by mitigating switch subthreshold leakage and bulk leakage. Its novel transmission-gate topology achieves wide-swing performance. Though only consuming 100 pico-Watts, it achieves a precision of 7.6 effective number of bits (ENOB). The track-and-hold amplifier was designed in 130-nm CMOS

Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step

Design and analysis techniques for nano-joule ADCs and sampling linearity

Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling network. Low energy analog design techniques for emerging systems powered by energy scavenging are demonstrated in the context of an analog-to-digital converter system. It is composed of a variable gain sample-and-hold amplifier, a low voltage reference, a 1.5 bit per stage 9-b cyclic ADC, clock generation, reference buffers, and control logic. A novel Class-AB current mirror amplifier together with correlated level shifting enable wide swing and enhanced gain operation at low supply voltages while reducing current draw. The use of subthreshold MOSFETs instead of bipolar junction transistors allows the use of traditional bandgap circuit techniques to be employed for a 530 mV reference that is less than a diode voltage drop. Operating from a 750 mV supply voltage and 20.48 kSPS, the ADC and reference consume 9.5μA and 1.5μA, respectively. The measured 7.9-bit ENOB results in an FoM of 2.24 pJ/step. The total energy consumption is 535 pJ per conversion for the entire system. A novel model predicts tracking nonlinearity (NL) in the form of harmonic distortion (HD) for weakly NL (i.e. SFDR>30dBc) first order open-loop sampling circuits. The mechanisms for the NL are exponential settling, amplitude modulation, phase modulation and discrete-time modulation. The model demonstrates that HD typically increases at 20 dB per decade over most standard operating ranges and is a function of input frequency, sampling bandwidth, input amplitude, the sample rate and component nonlinearity. Application of the model is reduced to the equivalent of frequency-independent nonlinearity analysis over this range, requiring only a Taylor series expansion of the NL time constant. Design insight is given for common MOS switch types, revealing a high correlation between HD and bandwidth. The first method to quantify the trade-off between thermal noise (SNR) and linearity (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4, and HD5 versus frequency at multiple sample rates of a Sample and Hold test chip fabricated in a 0.25μm 1P5M CMOS process and Spectre simulation results support the findings. The results broadly apply to switched capacitor circuits in general and sampling circuits specifically, regardless of technology