1,284 research outputs found
Graphene-based spintronic components
A major challenge of spintronics is in generating, controlling and detecting
spin-polarized current. Manipulation of spin-polarized current, in particular,
is difficult. We demonstrate here, based on calculated transport properties of
graphene nanoribbons, that nearly +-100% spin-polarized current can be
generated in zigzag graphene nanoribbons (ZGNRs) and tuned by a source-drain
voltage in the bipolar spin diode, in addition to magnetic configurations of
the electrodes. This unusual transport property is attributed to the intrinsic
transmission selection rule of the spin subbands near the Fermi level in ZGNRs.
The simultaneous control of spin current by the bias voltage and the magnetic
configurations of the electrodes provides an opportunity to implement a whole
range of spintronics devices. We propose theoretical designs for a complete set
of basic spintronic devices, including bipolar spin diode, transistor and logic
gates, based on ZGNRs.Comment: 14 pages, 4 figure
A Sound and Complete Axiomatization of Majority-n Logic
Manipulating logic functions via majority operators recently drew the
attention of researchers in computer science. For example, circuit optimization
based on majority operators enables superior results as compared to traditional
logic systems. Also, the Boolean satisfiability problem finds new solving
approaches when described in terms of majority decisions. To support computer
logic applications based on majority a sound and complete set of axioms is
required. Most of the recent advances in majority logic deal only with ternary
majority (MAJ- 3) operators because the axiomatization with solely MAJ-3 and
complementation operators is well understood. However, it is of interest
extending such axiomatization to n-ary majority operators (MAJ-n) from both the
theoretical and practical perspective. In this work, we address this issue by
introducing a sound and complete axiomatization of MAJ-n logic. Our
axiomatization naturally includes existing majority logic systems. Based on
this general set of axioms, computer applications can now fully exploit the
expressive power of majority logic.Comment: Accepted by the IEEE Transactions on Computer
Non-Volatile Magnonic Logic Circuits Engineering
We propose a concept of magnetic logic circuits engineering, which takes an
advantage of magnetization as a computational state variable and exploits spin
waves for information transmission. The circuits consist of magneto-electric
cells connected via spin wave buses. We present the result of numerical
modeling showing the magneto-electric cell switching as a function of the
amplitude as well as the phase of the spin wave. The phase-dependent switching
makes it possible to engineer logic gates by exploiting spin wave buses as
passive logic elements providing a certain phase-shift to the propagating spin
waves. We present a library of logic gates consisting of magneto-electric cells
and spin wave buses providing 0 or p phase shifts. The utilization of phases in
addition to amplitudes is a powerful tool which let us construct logic circuits
with a fewer number of elements than required for CMOS technology. As an
example, we present the design of the magnonic Full Adder Circuit comprising
only 5 magneto-electric cells. The proposed concept may provide a route to more
functional wave-based logic circuitry with capabilities far beyond the limits
of the traditional transistor-based approach
Weighted p-bits for FPGA implementation of probabilistic circuits
Probabilistic spin logic (PSL) is a recently proposed computing paradigm
based on unstable stochastic units called probabilistic bits (p-bits) that can
be correlated to form probabilistic circuits (p-circuits). These p-circuits can
be used to solve problems of optimization, inference and also to implement
precise Boolean functions in an "inverted" mode, where a given Boolean circuit
can operate in reverse to find the input combinations that are consistent with
a given output. In this paper we present a scalable FPGA implementation of such
invertible p-circuits. We implement a "weighted" p-bit that combines stochastic
units with localized memory structures. We also present a generalized tile of
weighted p-bits to which a large class of problems beyond invertible Boolean
logic can be mapped, and how invertibility can be applied to interesting
problems such as the NP-complete Subset Sum Problem by solving a small instance
of this problem in hardware
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