2,616 research outputs found

    The Realization of Redistribution Layers for FOWLP by Inkjet Printing

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    The implementation of additive manufacturing technology (e.g., digital printing) to the electronic packaging segment has recently received increasing attention. In almost all types of Fan-out wafer level packaging (FOWLP), redistribution layers (RDLs) are formed by a combination of photolithography, sputtering and plating process. Alternatively, in this study, inkjet-printed RDLs were introduced for FOWLP. In contrast to a subtractive method (e.g., photolithography), additive manufacturing techniques allow depositing the material only where it is desired. In the current study, RDL structures for different embedded modules were realized by inkjet printing and further characterized by electrical examinations. It was proposed that a digital printing process can be a more efficient and lower-cost solution especially for rapid prototyping of RDLs, since several production steps will be skipped, less material will be wasted and the supply chain will be shortened.EC/H2020/737487/EU/(Ultra)Sound Interfaces and Low Energy iNtegrated SEnsors/SILENS

    High yield fabrication process for 3D-stacked ultra-thin chip packages using photo-definable polyimide and symmetry in packages

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    Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. At first thinned dies are embedded in a polyimide interposer with a fine-pitch metal fan-out resulting Ultra-Thin Chip Packages (UTCP), next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by introduction of an additional layer of interposer which makes it flat at the chip edge and thus the whole packages is named as “Flat-UTCP”. In addition to that, randomness in non-functional package positions per panel reduces the overall yield of the whole process up to certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of 4 EEPROM dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield

    3D-stacking of ultra-thin chips and chip packages

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    Microsystems technology: objectives

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    This contribution focuses on the objectives of microsystems technology (MST). The reason for this is two fold. First of all, it should explain what MST actually is. This question is often posed and a simple answer is lacking, as a consequence of the diversity of subjects that are perceived as MST. The second reason is that a map of the somewhat chaotic field of MST is needed to identify sub-territories, for which standardization in terms of system modules an interconnections is feasible. To define the objectives a pragmatic approach has been followed. From the literature a selection of topics has been chosen and collected that are perceived as belonging to the field of MST by a large community of workers in the field (more than 250 references). In this way an overview has been created with `applicationsÂż and `generic issuesÂż as the main characteristics

    Glass-Embedded Fan-Out Antenna-in-Packaging for 5G Millimeter Wave Applications

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    The paper proposes a novel Antenna-in-Packaging (AiP) structure design for 60 GHz, millimeter wave WiFi applications. In the AiP design, single- or double-sided glass redistribution layers were embedded in a typical fan-out (FO) packaging structure to introduce design flexibility and to improve the radiation properties of the antenna. ANSYS-HFSS software was employed for electromagnetic (EM) characteristic simulations on the fan-out AiP (FO_AiP) design. To improve antenna radiation performance, single factor analyses were first performed to study the impact of each of the design parameters. A consecutive procedure followed to find more suitable combinations of the design parameters. As a result, two typical glass-embedded FO_AiP structures - one with 7.6 GHz bandwidth plus 4.7 dB gain and upward radiation, and another with 5.3 GHz bandwidth plus 5.2 dB gain and downward radiation, are proposed for the 60 GHz applications

    3D Stretchable Arch Ribbon Array Fabricated via Grayscale Lithography.

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    Microstructures with flexible and stretchable properties display tremendous potential applications including integrated systems, wearable devices and bio-sensor electronics. Hence, it is essential to develop an effective method for fabricating curvilinear and flexural microstructures. Despite significant advances in 2D stretchable inorganic structures, large scale fabrication of unique 3D microstructures at a low cost remains challenging. Here, we demonstrate that the 3D microstructures can be achieved by grayscale lithography to produce a curved photoresist (PR) template, where the PR acts as sacrificial layer to form wavelike arched structures. Using plasma-enhanced chemical vapor deposition (PECVD) process at low temperature, the curved PR topography can be transferred to the silicon dioxide layer. Subsequently, plasma etching can be used to fabricate the arched stripe arrays. The wavelike silicon dioxide arch microstructure exhibits Young modulus and fracture strength of 52 GPa and 300 MPa, respectively. The model of stress distribution inside the microstructure was also established, which compares well with the experimental results. This approach of fabricating a wavelike arch structure may become a promising route to produce a variety of stretchable sensors, actuators and circuits, thus providing unique opportunities for emerging classes of robust 3D integrated systems

    Glass-Embedded Fan-Out Antenna-in-Packaging for 5G Millimeter Wave Applications

    Get PDF
    The paper proposes a novel Antenna-in-Packaging (AiP) structure design for 60 GHz, millimeter wave WiFi applications. In the AiP design, single- or double-sided glass redistribution layers were embedded in a typical fan-out (FO) packaging structure to introduce design flexibility and to improve the radiation properties of the antenna. ANSYS-HFSS software was employed for electromagnetic (EM) characteristic simulations on the fan-out AiP (FO_AiP) design. To improve antenna radiation performance, single factor analyses were first performed to study the impact of each of the design parameters. A consecutive procedure followed to find more suitable combinations of the design parameters. As a result, two typical glass-embedded FO_AiP structures - one with 7.6 GHz bandwidth plus 4.7 dB gain and upward radiation, and another with 5.3 GHz bandwidth plus 5.2 dB gain and downward radiation, are proposed for the 60 GHz applications

    Design, Extraction, and Optimization Tool Flows and Methodologies for Homogeneous and Heterogeneous Multi-Chip 2.5D Systems

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    Chip and packaging industries are making significant progress in 2.5D design as a result of increasing popularity of their application. In advanced high-density 2.5D packages, package redistribution layers become similar to chip Back-End-of-Line routing layers, and the gap between them scales down with pin density improvement. Chiplet-package interactions become significant and severely affect system performance and reliability. Moreover, 2.5D integration offers opportunities to apply novel design techniques. The traditional die-by-die design approach neither carefully considers these interactions nor fully exploits the cross-boundary design opportunities. This thesis presents chiplet-package cross-boundary design, extraction, analysis, and optimization tool flows and methodologies for high-density 2.5D packaging technologies. A holistic flow is presented that can capture all parasitics from chiplets and the package and improve system performance through iterative optimizations. Several design techniques are demonstrated for agile development and quick turn-around time. To validate the flow in silicon, a chip was taped out and studied in TSMC 65nm technology. As the holistic flow cannot handle heterogeneous technologies, in-context flows are presented. Three different flavors of the in-context flow are presented, which offer trade-offs between scalability and accuracy in heterogeneous 2.5D system designs. Inductance is an inseparable part of a package design. A holistic flow is presented that takes package inductance into account in timing analysis and optimization steps. Custom CAD tools are developed to make these flows compatible with the industry standard tools and the foundry model. To prove the effectiveness of the flows several design cases of an ARM Cortex-M0 are implemented for comparitive study

    ADAPTIVE PATTERNING FOR PANELIZED PACKAGING

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    ABSTRACT Fan-Out Wafer-Level Packaging (FOWLP) or fan-out technology has held promise for a number of years; primarily as a means of packaging semiconductor devices with interconnect densities exceeding the capabilities of standard Wafer Level Chip Scale Packaging (WLCSP). With FOWLP technology, die are embedded in a molded panel, and I/Os are then redistributed over the larger effective surface area using conventional WLCSP techniques. The packages are then singulated and attached directly to a printed circuit board (PCB) or lowcost substrate. This technology provides one of the smallest and lightest possible package form factors; enables more I/Os for a given pitch with excellent electrical properties; and eliminates the need for custom substrates used in flip chip or wirebond Ball Grid Array (BGA) packages. Despite its promise, widespread adoption of FOWLP packaging has been limited largely by cost and yield issues. The requirement for high die placement accuracy when forming the molded panel restricts throughput at the die pick-and-place operation, leading to high process costs. Die drift, or movement during panel molding, limits via and RDL design rules and ultimately can result in yield loss when the drift is excessive. Managing or overcoming die offset is one of the keys to making FOWLP competitive with other package formats. This paper describes an approach to FOWLP that allows die offset to increase by an order of magnitude compared with conventional methods. Using a novel Adaptive Patterning* technology, real-time designs are created for each package within each panel during the manufacturing process. After panelization, the position of each die within each molded panel is precisely measured. Information is fed into a proprietary auto-routing design tool on a per panel basis. The resulting pattern layers are then issued to a lithography system which dynamically implements the unique design on a per panel basis. Dynamic layers include various design features such as vias or redistribution layers (RDL). The ability of adaptive patterning to correct for deviations in die location can result in both improved yield and higher panelization throughput, thereby enabling the industry to finally realize the cost, flexibility, and form factor benefits of FOWLP. In the paper, adaptive patterning examples will be presented and the benefits and limitations of the technology will be discussed
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