355 research outputs found
Spectral Signature Analysis โ BIST for RF Front-Ends
In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test โ BIST) for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver) on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC) at critical building blocks
Frequency diversity wideband digital receiver and signal processor for solid-state dual-polarimetric weather radars
2012 Summer.Includes bibliographical references.The recent spate in the use of solid-state transmitters for weather radar systems has unexceptionably revolutionized the research in meteorology. The solid-state transmitters allow transmission of low peak powers without losing the radar range resolution by allowing the use of pulse compression waveforms. In this research, a novel frequency-diversity wideband waveform is proposed and realized to extenuate the low sensitivity of solid-state radars and mitigate the blind range problem tied with the longer pulse compression waveforms. The latest developments in the computing landscape have permitted the design of wideband digital receivers which can process this novel waveform on Field Programmable Gate Array (FPGA) chips. In terms of signal processing, wideband systems are generally characterized by the fact that the bandwidth of the signal of interest is comparable to the sampled bandwidth; that is, a band of frequencies must be selected and filtered out from a comparable spectral window in which the signal might occur. The development of such a wideband digital receiver opens a window for exciting research opportunities for improved estimation of precipitation measurements for higher frequency systems such as X, Ku and Ka bands, satellite-borne radars and other solid-state ground-based radars. This research describes various unique challenges associated with the design of a multi-channel wideband receiver. The receiver consists of twelve channels which simultaneously downconvert and filter the digitized intermediate-frequency (IF) signal for radar data processing. The product processing for the multi-channel digital receiver mandates a software and network architecture which provides for generating and archiving a single meteorological product profile culled from multi-pulse profiles at an increased data date. The multi-channel digital receiver also continuously samples the transmit pulse for calibration of radar receiver gain and transmit power. The multi-channel digital receiver has been successfully deployed as a key component in the recently developed National Aeronautical and Space Administration (NASA) Global Precipitation Measurement (GPM) Dual-Frequency Dual-Polarization Doppler Radar (D3R). The D3R is the principal ground validation instrument for the precipitation measurements of the Dual Precipitation Radar (DPR) onboard the GPM Core Observatory satellite scheduled for launch in 2014. The D3R system employs two broadly separated frequencies at Ku- and Ka-bands that together make measurements for precipitation types which need higher sensitivity such as light rain, drizzle and snow. This research describes unique design space to configure the digital receiver for D3R at several processing levels. At length, this research presents analysis and results obtained by employing the multi-carrier waveforms for D3R during the 2012 GPM Cold-Season Precipitation Experiment (GCPEx) campaign in Canada
Analog Block Evaluation with BIST Instruments
The demands for quality and for the ability to compete in the market make it necessary not only to facilitate the testing of analog circuits but also to make them more efficient. With the increase in systems complexity and level of integration, the process of testing analog circuits has become difficult and expensive. This dissertation, proposed by Synopsys Portugal, aims to perform a study on analog Built-In Self-Test (BIST) and implement a simple analog BIST system that is capable of testing a voltage regulator and an oscillator on specifics parameters. In the regulator, the parameters to test are: Over and Under Voltage, Settling Time and Voltage Ripple.
In the oscillator the parameters to test are:
Frequency Drift, Settling Time and Duty-Cycle Distortion.
This methodology allows for self-test operations and, thus, reduces complexity and cost associated with performing analog circuit tests. It makes it possible to test the circuits periodically throughout its lifetime and also monitors some analog parameters in real-time
ํ์ค ๊ธฐ๋ฐ ํผ๋ ํฌ์๋ ์ดํ๋ผ์ด์ ๋ฅผ ๊ฐ์ถ ๊ณ ์ฉ๋ DRAM์ ์ํ ์ปจํธ๋กค๋ฌ PHY ์ค๊ณ
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ) -- ์์ธ๋ํ๊ต ๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2020. 8. ๊น์ํ.A controller PHY for managed DRAM solution, which is a new memory structure to maximize capacity while minimizing refresh power, is presented. Inter-symbol interference is critical in such a high-capacity DRAM interface in which many DRAM chips share a command/address (C/A) channel. A pulse-based feed-forward equalizer (PB-FFE) is introduced to reduce ISI on a C/A channel. The controller PHY supports all the training sequences specified in the DDR4 standard. A glitch-free DCDL is also adopted to perform link training efficiently and to reduce training time.
The DQ transmitter adopts quarter-rate architecture to reduce output latency. For the quarter-rate transmitters in DQ, we propose a quadrature error corrector (QEC), in which clock signal phase errors are corrected using two replicas of the 4:1 serializer of the output stage. Pulse shrinking is used to compare and equalize the outputs of these two replica serializers.
A controller PHY was fabricated in 55nm CMOS. The PB-FFE increases the timing margin from 0.23UI to 0.29UI at 1067Mbps. At 2133Mbps, the read timing and voltage margins are 0.53UI and 211mV after read training, and the write margins are 0.72UI and 230mV after write training.
To validate the QEC effectiveness, a prototype quarter-rate transmitter, including the QEC, was fabricated to another chip in 65nm CMOS. Adopting our QEC, the experimental results show that the output phase errors of the transmitter are reduced to a residual error of 0.8ps, and the output eye width and height are improved by 84% and 61%, respectively, at a data-rate of 12.8Gbps.๋ณธ ์ฐ๊ตฌ์์ ์ฉ๋์ ์ต๋ํํ๋ฉด์๋ ๋ฆฌํ๋ ์ ์ ๋ ฅ์ ์ต์ํํ ์ ์๋ ์๋ก์ด ๋ฉ๋ชจ๋ฆฌ ๊ตฌ์กฐ์ธ ๊ด๋ฆฌํ DRAM ์๋ฃจ์
์ ์ํ ์ปจํธ๋กค๋ฌ PHY๋ฅผ ์ ์ํ์๋ค. ์ด์ ๊ฐ์ ๊ณ ์ฉ๋ DRAM ์ธํฐํ์ด์ค์์๋ ๋ง์ DRAM ์นฉ์ด ๋ช
๋ น / ์ฃผ์ (C/A) ์ฑ๋์ ๊ณต์ ํ๊ณ ์์ด์ ์ฌ๋ณผ ๊ฐ ๊ฐ์ญ์ด ๋ฐ์ํ๋ค. ๋ณธ ์ฐ๊ตฌ์์๋ ์ด๋ฌํ C/A ์ฑ๋์์์ ์ฌ๋ณผ ๊ฐ ๊ฐ์ญ์ ์ค์ด๊ธฐ ์ํด ํ์ค ๊ธฐ๋ฐ ํผ๋ ํฌ์๋ ์ดํ๋ผ์ด์ (PB-FFE)๋ฅผ ์ฑํํ์๋ค. ๋ํ ๋ณธ ์ฐ๊ตฌ์ ์ปจํธ๋กค๋ฌ PHY๋ DDR4 ํ์ค์ ์ง์ ๋ ๋ชจ๋ ํธ๋ ์ด๋ ์ํ์ค๋ฅผ ์ง์ํ๋ค. ๋งํฌ ํธ๋ ์ด๋์ ํจ์จ์ ์ผ๋ก ์ํํ๊ณ ํธ๋ ์ด๋ ์๊ฐ์ ์ค์ด๊ธฐ ์ํด ๊ธ๋ฆฌ์น๊ฐ ๋ฐ์ํ์ง ์๋ ๋์งํธ ์ ์ด ์ง์ฐ ๋ผ์ธ (DCDL)์ ์ฑํํ์๋ค.
์ปจํธ๋กค๋ฌ PHY์ DQ ์ก์ ๊ธฐ๋ ์ถ๋ ฅ ๋๊ธฐ ์๊ฐ์ ์ค์ด๊ธฐ ์ํด ์ฟผํฐ ๋ ์ดํธ ๊ตฌ์กฐ๋ฅผ ์ฑํํ์๋ค. ์ฟผํฐ ๋ ์ดํธ ์ก์ ๊ธฐ์ ๊ฒฝ์ฐ์๋ ์ง๊ต ํด๋ญ ๊ฐ ์์ ์ค๋ฅ๊ฐ ์ถ๋ ฅ ์ ํธ์ ๋ฌด๊ฒฐ์ฑ์ ์ํฅ์ ์ฃผ๊ฒ ๋๋ค. ์ด๋ฌํ ์ํฅ์ ์ต์ํํ๊ธฐ ์ํด ๋ณธ ์ฐ๊ตฌ์์๋ ์ถ๋ ฅ ๋จ์ 4 : 1 ์ง๋ ฌ ๋ณํ๊ธฐ์ ๋ ๋ณต์ ๋ณธ์ ์ฌ์ฉํ์ฌ ํด๋ก ์ ํธ ์์ ์ค๋ฅ๋ฅผ ์์ ํ๋ QEC (Quadrature Error Corrector)๋ฅผ ์ ์ํ์๋ค. ๋ณต์ ๋ 2๊ฐ์ ์ง๋ ฌ ๋ณํ๊ธฐ์ ์ถ๋ ฅ์ ๋น๊ตํ๊ณ ๊ท ๋ฑํํ๊ธฐ ์ํด ํ์ค ์์ถ ์ง์ฐ ๋ผ์ธ์ด ์ฌ์ฉ๋์๋ค.
์ปจํธ๋กค๋ฌ PHY๋ 55nm CMOS ๊ณต์ ์ผ๋ก ์ ์กฐ๋์๋ค. PB-FFE๋ 1067Mbps์์ C/A ์ฑ๋ ํ์ด๋ฐ ๋ง์ง์ 0.23UI์์ 0.29UI๋ก ์ฆ๊ฐ์ํจ๋ค. ์ฝ๊ธฐ ํธ๋ ์ด๋ ํ ์ฝ๊ธฐ ํ์ด๋ฐ ๋ฐ ์ ์ ๋ง์ง์ 2133Mbps์์ 0.53UI ๋ฐ 211mV์ด๊ณ , ์ฐ๊ธฐ ํธ๋ ์ด๋ ํ ์ฐ๊ธฐ ๋ง์ง์ 0.72UI ๋ฐ 230mV์ด๋ค.
QEC์ ํจ๊ณผ๋ฅผ ๊ฒ์ฆํ๊ธฐ ์ํด QEC๋ฅผ ํฌํจํ ํ๋กํ ํ์
์ฟผํฐ ๋ ์ดํธ ์ก์ ๊ธฐ๋ฅผ 65nm CMOS์ ๋ค๋ฅธ ์นฉ์ผ๋ก ์ ์ํ์๋ค. QEC๋ฅผ ์ ์ฉํ ์คํ ๊ฒฐ๊ณผ, ์ก์ ๊ธฐ์ ์ถ๋ ฅ ์์ ์ค๋ฅ๊ฐ 0.8ps์ ์๋ฅ ์ค๋ฅ๋ก ๊ฐ์ํ๊ณ , ์ถ๋ ฅ ๋ฐ์ดํฐ ๋์ ํญ๊ณผ ๋์ด๊ฐ 12.8Gbps์ ๋ฐ์ดํฐ ์๋์์ ๊ฐ๊ฐ 84 %์ 61 % ๊ฐ์ ๋์์์ ๋ณด์ฌ์ค๋ค.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.1.1 HEAVY LOAD C/A CHANNEL 5
1.1.2 QUARTER-RATE ARCHITECTURE IN DQ TRANSMITTER 7
1.1.3 SUMMARY 8
1.2 THESIS ORGANIZATION 10
CHAPTER 2 ARCHITECTURE 11
2.1 MDS DIMM STRUCTURE 11
2.2 MDS CONTROLLER 15
2.3 MDS CONTROLLER PHY 17
2.3.1 INITIALIZATION SEQUENCE 20
2.3.2 LINK TRAINING FINITE-STATE MACHINE 23
2.3.3 POWER DOWN MODE 28
CHAPTER 3 PULSE-BASED FEED-FORWARD EQUALIZER 29
3.1 COMMAND/ADDRESS CHANNEL 29
3.2 COMMAND/ADDRESS TRANSMITTER 33
3.3 PULSE-BASED FEED-FORWARD EQUALIZER 35
CHAPTER 4 CIRCUIT IMPLEMENTATION 39
4.1 BUILDING BLOCKS 39
4.1.1 ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) 39
4.1.2 ALL-DIGITAL DELAY-LOCKED LOOP (ADDLL) 44
4.1.3 GLITCH-FREE DCDL CONTROL 47
4.1.4 DUTY-CYCLE CORRECTOR (DCC) 50
4.1.5 DQ/DQS TRANSMITTER 52
4.1.6 DQ/DQS RECEIVER 54
4.1.7 ZQ CALIBRATION 56
4.2 MODELING AND VERIFICATION OF LINK TRAINING 59
4.3 BUILT-IN SELF-TEST CIRCUITS 66
CHAPTER 5 QUADRATURE ERROR CORRECTOR USING REPLICA SERIALIZERS AND PULSE-SHRINKING DELAY LINES 69
5.1 PHASE CORRECTION USING REPLICA SERIALIZERS AND PULSE-SHRINKING UNITS 69
5.2 OVERALL QEC ARCHITECTURE AND ITS OPERATION 71
5.3 FINE DELAY UNIT IN THE PSDL 76
CHAPTER 6 EXPERIMENTAL RESULTS 78
6.1 CONTROLLER PHY 78
6.2 PROTOTYPE QEC 88
CHAPTER 7 CONCLUSION 94
BIBLIOGRAPHY 96Docto
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