Automated Hardware Prototyping for 3D Network on Chips

Vor mehr als 50 Jahren stellte Intel® Mitbegründer Gordon Moore eine Prognose zum Entwicklungsprozess der Transistortechnologie auf. Er prognostizierte, dass sich die Zahl der Transistoren in integrierten Schaltungen alle zwei Jahre verdoppeln wird. Seine Aussage ist immer noch gültig, aber ein Ende von Moores Gesetz ist in Sicht. Mit dem Ende von Moore’s Gesetz müssen neue Aspekte untersucht werden, um weiterhin die Leistung von integrierten Schaltungen zu steigern. Zwei mögliche Ansätze für "More than Moore” sind 3D-Integrationsverfahren und heterogene Systeme. Gleichzeitig entwickelt sich ein Trend hin zu Multi-Core Prozessoren, basierend auf Networks on chips (NoCs). Neben dem Ende des Mooreschen Gesetzes ergeben sich bei immer kleiner werdenden Technologiegrößen, vor allem jenseits der 60 nm, neue Herausforderungen. Eine Schwierigkeit ist die Wärmeableitung in großskalierten integrierten Schaltkreisen und die daraus resultierende Überhitzung des Chips. Um diesem Problem in modernen Multi-Core Architekturen zu begegnen, muss auch die Verlustleistung der Netzwerkressourcen stark reduziert werden. Diese Arbeit umfasst eine durch Hardware gesteuerte Kombination aus Frequenzskalierung und Power Gating für 3D On-Chip Netzwerke, einschließlich eines FPGA Prototypen. Dafür wurde ein Takt-synchrones 2D Netzwerk auf ein dreidimensionales asynchrones Netzwerk mit mehreren Frequenzbereichen erweitert. Zusätzlich wurde ein skalierbares Online-Power-Management System mit geringem Ressourcenaufwand entwickelt. Die Verifikation neuer Hardwarekomponenten ist einer der zeitaufwendigsten Schritte im Entwicklungsprozess hochintegrierter digitaler Schaltkreise. Um diese Aufgabe zu beschleunigen und um eine parallele Softwareentwicklung zu ermöglichen, wurde im Rahmen dieser Arbeit ein automatisiertes und benutzerfreundliches Tool für den Entwurf neuer Hardware Projekte entwickelt. Eine grafische Benutzeroberfläche zum Erstellen des gesamten Designablaufs, vom Erstellen der Architektur, Parameter Deklaration, Simulation, Synthese und Test ist Teil dieses Werkzeugs. Zudem stellt die Größe der Architektur für die Erstellung eines Prototypen eine besondere Herausforderung dar. Frühere Arbeiten haben es versäumt, eine schnelles und unkompliziertes Prototyping, insbesondere von Architekturen mit mehr als 50 Prozessorkernen, zu realisieren. Diese Arbeit umfasst eine Design Space Exploration und FPGA-basierte Prototypen von verschiedenen 3D-NoC Implementierungen mit mehr als 80 Prozessoren

Engineering Method and Tool for the Complete Virtual Commissioning of Robotic Cells

Intelligent robotic manufacturing cells must adapt to ever-varying operating conditions, developing autonomously optimal manufacturing strategies to achieve the best quality and overall productivity. Intelligent and cognitive behaviors are realized by using distributed controllers, in which complex control logics must interact and process a wide variety of input/output signals. In particular, programmable logic controllers (PLCs) and robot controllers must be coordinated and integrated. Then, there is the need to simulate the robotic cells’ behavior for performance verification and optimization by evaluating the effects of both PLC and robot control codes. In this context, this work proposes a method, and its implementation into an integrated tool, to exploit the potential of ABB RobotStudio software as a virtual prototyping platform for robotic cells, in which real robots control codes are executed on a virtual controller and integrated with Beckhoff PLC environment. For this purpose, a PLC Smart Component was conceived as an extension of RobotStudio functionalities to exchange signals with a TwinCAT instance. The new module allows the virtual commissioning of a complete robotic cell to be performed, assessing the control logics effects on the overall productivity. The solution is demonstrated on a robotic assembly cell, showing its feasibility and effectiveness in optimizing the final performance

3D PRINTING, OPEN-SOURCE TECHNOLOGY AND THEIR APPLICATIONS IN RESEARCH

Open-source software received tremendous success as it drives down the cost of software and expand the distribution. Open-source hardware, as part of the open-source movement, has just risen into public attention for its potential to further drive down the cost of all kinds of manufacturing goods and reshape the manufacture chain. In this report we explores the history, development and the future of open-source hardware project, summarizing the opportunities, challenges and possible solutions. 3D printing is demonstrated as a booster to assist open-source hardware’s development. Low-cost 3D printer enables at-home and in-time fabrication, the download-print-use-improve-distribute cycle is established to encourage more to make and in turn to benefit more. Researchers, teachers and scientists are the first to receive the benefit since they are often lack of budget to purchase much expensive research tools with only limited function. To demonstrate the power of open-source 3D printing in driving down research cost. A library of 3D printable optics components are designed, printed and tested. The study shows significantly reduced research cost – more than 97% equipment investment is saved with some of the optical parts representing only 1% of the cost of its commercial version. Cost reduction stimulates a much broader participants that can further help in modifying, improving the project or even developing new project, this is how open-source hardware innovation chain is established. In the end it is summarized as the technology advances, printers suitable for all kinds of material such as metals, bio-materials, semiconductors are become feasible, the open-source paradigm has the potential to replace the tradition manufacture and activate the new future

Integrated Platform for Whole Building HVAC System Automation and Simulation

Integrated optimal control strategies can reduce the overall building HVAC system energy consumption as well as improved air quality resulting in improved health and cognitive function for the occupants. However, it is time consuming to quantitatively evaluate the design-intended building HVAC automation system performance before on-site deployment, because: 1) the building and HVAC system design specs are in 2D or 3D drawings that require significant efforts to develop the system steady state or dynamic models based on them; 2) the building HVAC control strategies are designed and implemented in building automation (BA) system that could not smoothly connect with the building HVAC system steady state or dynamic models for performance evaluation through close-loop simulation. This paper presents the tool chain of an integrated simulation platform for building HVAC system automation and simulation as well as its implementation in a real case. First, building information from a Revit BIM model is automatically parsed to an EnergyPlus building energy model. Second, the HVAC system model is quickly populated with a scalable HVAC system library in Dymola. Third, the HVAC controls are developed in WebCTRL, a building HVAC automation system by Automated Logic Corporation (ALC). Finally, both the building energy model and HVAC system model are wrapped up as Functional Mock-up Units (FMU) and connected with embedded simulator in WebCTRL to perform close-loop building automation system performance simulation. A real case study, a chiller plant system in a hotel building, is conducted to verify the scalability and benefit of the developed tool chain. The case study demonstrates the values in identifying both HVAC automation system design-intended control issues and improvement areas for integrated optimal controls. This platform enables testing of building HVAC control strategies before on-site deployment, which reduces the labor and time required for building HVAC control development-to-market process and ensure the delivering quality. Furthermore, this platform can be calibrated with metered real-time data from the specific building HVAC system and serve as its “digital twin” that empowers the system fault detection, diagnostics and predictive maintenance

MPSoCBench : um framework para avaliação de ferramentas e metodologias para sistemas multiprocessados em chip

Orientador: Rodolfo Jardim de AzevedoTese (doutorado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: Recentes metodologias e ferramentas de projetos de sistemas multiprocessados em chip (MPSoC) aumentam a produtividade por meio da utilização de plataformas baseadas em simuladores, antes de definir os últimos detalhes da arquitetura. No entanto, a simulação só é eficiente quando utiliza ferramentas de modelagem que suportem a descrição do comportamento do sistema em um elevado nível de abstração. A escassez de plataformas virtuais de MPSoCs que integrem hardware e software escaláveis nos motivou a desenvolver o MPSoCBench, que consiste de um conjunto escalável de MPSoCs incluindo quatro modelos de processadores (PowerPC, MIPS, SPARC e ARM), organizado em plataformas com 1, 2, 4, 8, 16, 32 e 64 núcleos, cross-compiladores, IPs, interconexões, 17 aplicações paralelas e estimativa de consumo de energia para os principais componentes (processadores, roteadores, memória principal e caches). Uma importante demanda em projetos MPSoC é atender às restrições de consumo de energia o mais cedo possível. Considerando que o desempenho do processador está diretamente relacionado ao consumo, há um crescente interesse em explorar o trade-off entre consumo de energia e desempenho, tendo em conta o domínio da aplicação alvo. Técnicas de escalabilidade dinâmica de freqüência e voltagem fundamentam-se em gerenciar o nível de tensão e frequência da CPU, permitindo que o sistema alcance apenas o desempenho suficiente para processar a carga de trabalho, reduzindo, consequentemente, o consumo de energia. Para explorar a eficiência energética e desempenho, foram adicionados recursos ao MPSoCBench, visando explorar escalabilidade dinâmica de voltaegem e frequência (DVFS) e foram validados três mecanismos com base na estimativa dinâmica de energia e taxa de uso de CPUAbstract: Recent design methodologies and tools aim at enhancing the design productivity by providing a software development platform before the definition of the final Multiprocessor System on Chip (MPSoC) architecture details. However, simulation can only be efficiently performed when using a modeling and simulation engine that supports system behavior description at a high abstraction level. The lack of MPSoC virtual platform prototyping integrating both scalable hardware and software in order to create and evaluate new methodologies and tools motivated us to develop the MPSoCBench, a scalable set of MPSoCs including four different ISAs (PowerPC, MIPS, SPARC, and ARM) organized in platforms with 1, 2, 4, 8, 16, 32, and 64 cores, cross-compilers, IPs, interconnections, 17 parallel version of software from well-known benchmarks, and power consumption estimation for main components (processors, routers, memory, and caches). An important demand in MPSoC designs is the addressing of energy consumption constraints as early as possible. Whereas processor performance comes with a high power cost, there is an increasing interest in exploring the trade-off between power and performance, taking into account the target application domain. Dynamic Voltage and Frequency Scaling techniques adaptively scale the voltage and frequency levels of the CPU allowing it to reach just enough performance to process the system workload while meeting throughput constraints, and thereby, reducing the energy consumption. To explore this wide design space for energy efficiency and performance, both for hardware and software components, we provided MPSoCBench features to explore dynamic voltage and frequency scalability (DVFS) and evaluated three mechanisms based on energy estimation and CPU usage rateDoutoradoCiência da ComputaçãoDoutora em Ciência da Computaçã