183 research outputs found
Current and Voltage Mode Multiphase Sinusoidal Oscillators Using CBTAs
Current-mode (CM) and voltage-mode (VM) multiphase sinusoidal oscillator (MSO) structures using current backward transconductance amplifier (CBTA) are proposed. The proposed oscillators can generate n current or voltage signals (n being even or odd) equally spaced in phase. n+1 CBTAs, n grounded capacitors and a grounded resistor are used for nth-state oscillator. The oscillation frequency can be independently controlled through transconductance (gm) of the CBTAs which are adjustable via their bias currents. The effects caused by the non-ideality of the CBTA on the oscillation frequency and condition have been analyzed. The performance of the proposed circuits is demonstrated on third-stage and fifth-stage MSOs by using PSPICE simulations based on the 0.25 µm TSMC level-7 CMOS technology parameters
Digital PLL for ISM applications
In modern transceivers, a low power PLL is a key block. It is known that with the
evolution of technology, lower power and high performance circuitry is a challenging
demand.
In this thesis, a low power PLL is developed in order not to exceed 2mW of total power
consumption. It is composed by small area blocks which is one of the main demands.
The blocks that compose the PLL are widely abridged and the final solution is shown,
showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with
a frequency range from 400MHz to 1.5GHz, with a 300μW to approximately 660μW
power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming
a divide-by-64 divider. The Phase-Detector is a Dual D Flip-Flop detector with a charge
pump. The PLL has less than a 2us lock time and presents a output oscillation of 1GHz,
as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the
specifications.
The main contributions of this thesis are that this PLL can be applied in ISM applications
due to its covering frequency range and low cost 130nm CMOS technology
Oversampled analog-to-digital converter architectures based on pulse frequency modulation
Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development
of voltage-controlled oscillator based analog-to-digital converters (VCO-based
ADCs). Time-encoding based ADCs have become of great interest to the designer
community due to the possibility of implementing mostly digital circuits,
which are well suited for current deep-submicron CMOS processes. Within this
topic, VCO-based ADCs are one of the most promising candidates.
VCO-based ADCs have typically been analyzed considering the output phase
of the oscillator as a state variable, similar to the state variables considered in __
modulation loops. Although this assumption might take us to functional designs
(as verified by literature), it does not take into account neither the oscillation
parameters of the VCO nor the deterministic nature of quantization noise. To
overcome this issue, we propose an interpretation of these type of systems based
on the pulse frequency modulation (PFM) theory. This permits us to analytically
calculate the quantization noise, in terms of the working parameters of the system.
We also propose a linear model that applies to VCO-based systems. Thanks to
it, we can determine the different error processes involved in the digitization of
the input data, and the performance limitations which these processes direct to.
A generic model for any order open-loop VCO-based ADCs is made based on the
PFM theory. However, we will see that only the first-order case and a second order
approximation can be implemented in practice. The PFM theory also
allows us to propose novel approaches to both single-stage and multistage VCObased
architectures. We describe open-loop architectures such as VCO-based
architectures with digital precoding, PFM-based architectures that can be used
as efficient ADCs or MASH architectures with optimal noise-transfer-function
(NTF) zeros. We also make a first approach to the proposal and analysis of closed loop
architectures. At the same time, we deal with one of the main limitations of
VCOs (especially those built with ring oscillators), which is the non-linear voltage to-
frequency relation. In this document, we describe two techniques mitigate this
phenomenon.
Firstly, we propose to use a pulse width modulator in front of the VCO. This
way, there are only two possible oscillation states. Consequently, the oscillator
works linearly. To validate the proposed technique, an experimental prototype
was implemented in a 40-nm CMOS process. The chip showed noise problems
that degraded the expected resolution, but allowed us to verify that the potential
performance was close to the expected one. A potential signal-to-noise-distortion
ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming
2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar
power consumption and linearity properties.
Secondly, we used a pulse frequency modulator to implement a second ADC.
The proposed architecture is intrinsically linear and uses a digital delay line to
increase the resolution of the converter. One experimental prototype was implemented
in a 40-nm CMOS process using one of these architectures. Proper results
were measured from this prototype. These results allowed us to verify that the
PFM-based architecture could be used as an efficient ADC. The measured peak
SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an
occupied area equal to 0.08 mm2. The architecture shows a great linearity, and
in comparison to related work, it consumes less power and occupies similar area.
In general, the theoretical analyses and the architectures proposed in the
document are not restricted to any application. Nevertheless, in the case of the
experimental chips, the specifications required for these converters were linked to
communication applications (e.g. VDSL, VDSL2, or even G.fast), which means
medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low
area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva
para el diseño de convertidores analógico-digitales basados en osciladores
controlados por tensión. Los convertidores analógico-digitales con codificación
temporal han llamado la atención durante los últimos años de la comunidad de
diseñadores debido a la posibilidad de implementarlos en su gran mayoría con
circuitos digitales, los cuales son muy apropiados para los procesos de diseño
manométricos. En este ámbito, los convertidores analógico-digitales basados en
osciladores controlados por tensión son uno de los candidatos más prometedores.
Los convertidores analógico-digitales basados en osciladores controlados por
tensión han sido típicamente analizados considerando que la fase del oscilador
es una variable de estado similar a las que se observan en los moduladores __.
Aunque esta consideración puede llevarnos a diseños funcionales (como se puede
apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni
los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de
la modulación por frecuencia de pulsos. Esto nos permite calcular de forma
analítica las ecuaciones que modelan el ruido de cuantificación en función de los
parámetros de oscilación. Se propone también un modelo lineal para el análisis de
convertidores analógico-digitales basados en osciladores controlados por tensión.
Este modelo permite determinar las diferentes fuentes de error que se producen
durante el proceso de digitalización de los datos de entrada y las limitaciones
que suponen. Un modelo genérico de convertidor de cualquier orden se propone
con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una
aproximación al caso de segundo orden se pueden implementar en la práctica.
La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas
para la propuesta y el análisis tanto de arquitecturas de una sola etapa
como de arquitecturas de varias etapas construidas con osciladores controlados
por tensión. Se proponen y se describen arquitecturas en lazo abierto como son
las basadas en osciladores controlador por tensión con moduladores digitales en
la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como
convertidores analógico-digitales eficientes o arquitecturas en cascada en las que
se optimizan la distribución de los ceros en la función de transferencia del ruido.
También se realiza una aproximación a la propuesta y el análisis de arquitecturas
en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes
de los osciladores controlados por tensión (especialmente en aquellos
implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos
técnicas cuyo objetivo es mitigar esta limitación.
La primera técnica de corrección se basa en el uso de un modulador por
ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo
existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y
no se genera distorsión en los datos de salida. La técnica se propone de forma
teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo
la validación de la propuesta teórica se fabricó un prototipo experimental en un
proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la
resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá
haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una
potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de
banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con
sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo
que se mantiene el consumo así como la linealidad.
A continuación, se propone la implementación de un convertidor analógico digital
mediante un modulador por frecuencia de pulsos. La arquitectura propuesta
es intrínsecamente lineal y hace uso de una línea de retraso digital con
el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental,
se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura,
de la que se obtuvieron resultados notables. Estos resultados permitieron
verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor
analógico-digital eficiente. La arquitectura consigue una relación real
señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo
de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en
comparación con arquitecturas equivalentes, el consumo es menor mientras que
el área ocupada se mantiene similar.
En general, las aportaciones propuestas en este documento se pueden aplicar a
cualquier tipo de aplicación, independientemente de los requisitos de resolución,
ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos
fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones
(VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media
(9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja
área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman
Analog Implementation of Fractional-Order Elements and Their Applications
With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical “integer” methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems
Techniques for Wideband All Digital Polar Transmission
abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
Reconnection–less Reconfigurable Fractional–Order Current–Mode Integrator Design with Simple Control
A design of a fractional-order (FO) integrator is introduced for operation of resulting solution in the current mode (CM). The solution of the integrator is based on the utilization of RC structures, but in comparison to other RC structure based FO designs, the proposed integrator offers the electronic control of the order. Moreover, the control of the proposed integrator does not require multiple specific and accurate values of the control voltages/currents in comparison to the topologies based on the approximation of the FO Laplacian operator. The electronic control of a gain level (gain adjustment) of the proposed integrator is available. The paper offers the results of Cadence IC6 (spectre) simulations and more importantly experimental measurements to support the presented design. The proposed integrator can be used to build various FO circuits as demonstrated by the utilization of the integrator into a structure of a frequency filter in order to provide FO characteristics
Analysis and design of sinusoidal quadrature RC-oscillators
Modern telecommunication equipment requires components that operate in many different frequency bands and support multiple communication standards, to cope with the growing demand for higher data rate. Also, a growing number of standards are adopting the use of spectrum efficient digital modulations, such as quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM). These modulation schemes require accurate quadrature oscillators, which makes the quadrature oscillator a key block in modern radio frequency (RF) transceivers. The wide tuning range characteristics of inductorless quadrature oscillators make them natural candidates, despite their higher phase noise, in comparison with LC-oscillators. This thesis presents a detailed study of inductorless sinusoidal quadrature oscillators. Three quadrature oscillators are investigated: the active coupling RC-oscillator, the novel capacitive coupling RCoscillator, and the two-integrator oscillator. The thesis includes a detailed analysis of the Van der Pol oscillator (VDPO). This is used as a base model oscillator for the analysis of the coupled oscillators. Hence, the three oscillators are approximated by the VDPO. From the nonlinear Van der Pol equations, the oscillators’ key parameters are obtained. It is analysed first the case without component mismatches and then the case with mismatches. The research is focused on determining the impact of the components’ mismatches on the oscillator key parameters: frequency, amplitude-, and quadrature-errors. Furthermore, the minimization of the errors by adjusting the circuit parameters is addressed. A novel quadrature RC-oscillator using capacitive coupling is proposed. The advantages of using the capacitive coupling are that it is noiseless, requires a small area, and has low power dissipation. The equations of the oscillation amplitude, frequency, quadrature-error, and amplitude mismatch are derived. The theoretical results are confirmed by simulation and by measurement of two prototypes fabricated in 130 nm standard complementary metal-oxide-semiconductor (CMOS) technology. The measurements reveal that the power increase due to the coupling is marginal, leading to a figure-of-merit of -154.8 dBc/Hz. These results are consistent with the noiseless feature of this coupling and are comparable to those of the best state-of-the-art RC-oscillators, in the GHz range, but with the lowest power consumption (about 9 mW). The results for the three oscillators show that the amplitude- and the quadrature-errors
are proportional to the component mismatches and inversely proportional to the coupling strength.
Thus, increasing the coupling strength decreases both the amplitude- and quadrature-errors. With proper coupling strength, a quadrature error below 1° and amplitude imbalance below 1% are obtained. Furthermore, the simulations show that increasing the coupling strength reduces the phase noise. Hence, there is no trade-off between phase noise and quadrature error. In the twointegrator oscillator study, it was found that the quadrature error can be eliminated by adjusting the transconductances to compensate the capacitance mismatch. However, to obtain outputs in perfect quadrature one must allow some amplitude error
A low phase noise ring oscillator phase-locked loop for wireless applications
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 129).This thesis describes the circuit level design of a 900MHz [Sigma][Detta] ring oscillator based phase-locked loop using 0.35[mu]m technology. Multiple phase noise theories are considered giving insight into low phase-noise voltage controlled oscillator design. The circuit utilizes a fully symmetric differential voltage controlled oscillator with cascode current starved inverters to reduces current noise. A compact multi-modulus prescaler is presented, based on modified true single-phase clock flip-flops with integrated logic. A fully differential charge pump with switched-capacitor common mode feedback is utilized in conjunction with a nonlinear phase-frequency detector for accelerated acquisition time.by Colin Weltin-Wu.M.Eng
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