Physics and Technology of Silicon Carbide Devices

Recently, some SiC power devices such as Schottky-barrier diodes (SBDs), metal-oxide-semiconductor field-effect-transistors (MOSFETs), junction FETs (JFETs), and their integrated modules have come onto the market. However, to stably supply them and reduce their cost, further improvements for material characterizations and those for device processing are still necessary. This book abundantly describes recent technologies on manufacturing, processing, characterization, modeling, and so on for SiC devices. In particular, for explanation of technologies, I was always careful to argue physics underlying the technologies as much as possible. If this book could be a little helpful to progress of SiC devices, it will be my unexpected happiness

Epitaxial Graphene and its Electronic Device Applications

Department of Electrical EngineeringGraphene is a two-dimensional material in which carbon atoms are bonded in honeycomb lattice. It has a unique electronic band structure that shows zero band gap energy and linear dispersion relation near the Dirac point. Because of to its outstanding electrical and mechanical properties, graphene has been actively studied in various fields. After successfully separating graphene from highly oriented pyrolytic graphite (HOPG), a variety of methods for obtaining high quality and large area graphene have been studied. Especially, a method of growing epitaxial graphene (EG) on a SiC substrate has attracted much attention as a material for next generation electronic devices. This allows the growth of large area graphene and it is not necessary for transfer process because semi-insulating SiC wafer can be used as a substrate. However, it has disadvantages of requiring high temperature (> 1300 ??C) for high quality EG growth and the single crystalline SiC substrate are too expensive. In order to overcome these problem, we propose two effective methods for growth of EG on SiC. Firstly, the high quality EG is grown on 4H-, 6H SiC substrate by molybdenum plate (Mo-plate) capping during annealing process. Mo-plate capping causes the heat accumulation on SiC surface by preventing loss of thermal radiations from SiC surface, and increase the Si vapor pressure on SiC surface by enclosing the sublimated Si atoms. Therefore, the temperature of the SiC surface becomes higher than surrounding temperature, and the Si sublimation rate is reduced. These factors enable high quality EG growth at relatively low power assumption (chamber temperature). The quality enhancement of the grown EG with Mo-plate capping is demonstrated by Raman spectra, compared to EG without Moplate capping. Secondly, the graphene is formed on SiC thin film surface at relatively low temperature by electron beam (e-beam) irradiation with low acceleration voltage. The e-beam irradiation with low acceleration voltage induces the heat accumulation within several layers of SiC thin film surface due to its shallow penetration depth. The thermalized electrons weaken the bond strength of the Si-C atoms while staying within a few layers of SiC thin film surface, which reduce the heat energy required for sublimating Si atoms. As the electron fluency increase, the crystallinity and uniformity of grown graphene are improved, which is confirmed by Raman spectra and scanning electron microscopy (SEM) images. We propose the cleanly patterning method for graphene using Al thin film as etching mask because general patterning methods such as electron beam lithography and photolithography induce the degradation of graphene quality due to polymer residue. The properties of fabricated graphene device using Al thin film are confirmed by Hall measurement and Raman spectra, compared with graphene sample patterned with conventional photolithography. In particular, the apparent Shubnikov-de Haas (SdH) oscillation measured in graphene device patterned with Al thin film demonstrates better homogeneity and 2DEG system. The carrier density and Hall mobility in Al patterned EG device are measured to be 9.16 ?? 10^12 cm-2 and ~ 2100 cm2/Vs, respectively. The complementary logic inverter having graphene channel is fabricated by using selective doping of graphene. Ti or Al adsorbed graphene is doped n-type, because Ti or Al with lower work function than graphene induces the charge transfer from the Ti or Al to graphene. On the other hand, the SiO2 adsorbed graphene is doped to p-type by the dangling bonds of SiO2 surface. The doping concentration and type of graphene are confirmed by Raman spectra and electrical measurements. We fabricated two kinds of inverter doped with Al-SiO2 and Ti-SiO2 materials. These inverters exhibit a clear voltage inversion as function of Vin at a wide range of VDD from 0.5 V to 20 V, and the highest voltage gains are ~0.93 and ~0.86, respectively. These properties can be improved by using insulating layer of higher dielectric constant and reducing thickness of gate oxide. We propose a new structure of multifunctional capacitive sensor to surmount the limitations the previous single-capacitor sensor. The proposed dual-capacitor sensor composes of two capacitors stacking vertically in a pixel which detects strength information and surface-normal directionality of external stimuli, and clearly classifies the types of stimuli. These properties have been demonstrated by detecting and distinguishing the curvature, pressure, touch and strain stimuli through the capacitances changes of the two capacitors. We successfully fabricated a stable n-type InAs NW FET with a very simple fabrication process using pre-deposition of Al2O3 layer. This oxide layer of 10 nm thickness is uniformly formed on entire surface of NW channel by ALD. It serves not only as a gate oxide but also as a protective layer of the NW channel. The structure of completed device is demonstrated by TEM images and EDX electron mapping. The n-InAs NW FET shows good current saturation and low voltage operation, the peak transconductance (gm) is extracted to be 13.4 mS/mm, the field effect mobility (??FE) is calculated to be ~1039 cm2/Vs at VDS = 0.8 V and current on/off ratio is about ~750.ope

Characterization of low pressure chemically vapor deposited Boron Nitride films as low dielectric constant materials

Boron nitride thin films were synthesized on Si and quartz wafers by low pressure chemical vapor deposition using borane triethylamine complex and ammonia as precursors. The films were processed at 400°C, 475°C and 550°C at a constant pressure of 0.5 Torr and at different precursor flow ratios. The films deposited were uniform, amorphous and the composition of the films varied with deposition temperature and precursor flow ratios. The thickness of the film increased with increasing flow ratio, but, decreased with increasing temperature. The stresses in the film were either mildly tensile or compressive. The least dielectric constant for the films that could be attained was 2.73 at 550°C and at high flow ratios of NH3/TEAB (50/1). Thus, stoichiometric boron nitride films tend to have a lower dielectric constant. The limitation of attaining lower values could be due to the presence of carbon as an impurity in the film and the presence of mobile charge carriers in the films as well as at the substrate-film interface as seen from the capacitance-voltage characteristics

The Journal of Microelectronic Research 2005

https://scholarworks.rit.edu/meec_archive/1014/thumbnail.jp

A novel “in-situ” processed gate region on GaN MOS capacitors

This work reports a route to the realisation of GaN metal oxide semiconductor capacitors (MOSCAPs) where the GaN surface has not been exposed to atmosphere. This has been achieved by the deposition of a 5nm SiNx “capping” layer as the final part of the GaN on Si MOSCAP wafer growth to encapsulate the GaN surface, followed by its removal in a “cluster” plasma processing tool, which enables both etching of samples and subsequent dielectric and metal deposition without atmospheric exposure between process steps. Capacitance-voltage hysteresis, A Hysteresis, of 90mV and frequency dispersion, A dispersion, of 150mV were achieved from samples where the SiNx capping layer was etched and then transferred under vacuum prior to atomic layer deposition (ALD) of a 20 nm Al2O3 gate dielectric. These were lower than the previously reported values of 250mV and 350mV respectively for GaN-Al2O3 MOS capacitors where the GaN surface had been exposed to atmosphere. The effects of N2 and H2 plasma treatments after SiNx etch and prior to Al2O3 deposition were examined. Exposure to a 150W N2 plasma for 5 minutes produced a Hysteresis and a Dispersion of 200mV and 250mV respectively, both of which reduced to 60mVafter forming gas annealing (FGA) in 10% H2/90% N2 for 30 minutes at 430oC. The insertion of an ALD grown AlN interlayer between an air exposed GaN surface and the Al2O3 gate dielectric resulted in 50mV a Hysteresis and a Dispersion. However, when the process was transferred to samples that went through the SiNx etch and optimised N2 plasma pretreatment, both a Hysteresis and a Dispersion increased to 500mV. The effect of ALD deposition of a TiN gate metal after Al2O3 gate dielectric was also examined. SiNx capped samples were first etched in the cluster tool before transfer to the ALD chamber in which a 20nm Al2O3 gate dielectric was deposited. This was followed by atomic layer deposition of 20nm TiN gate metal. a Hysteresis and a Dispersion of 550mV and 400mV respectively were obtained. These samples had a capacitance-voltage slope which was 155% higher than otherwise comparable structures with Pt/Au gate metal. In conclusion the reductions in a Hysteresis and a Dispersion achieved in this work during in-situ etching and ALD are encouraging for the realisation of high power GaN devices

Synthesis and characterization of low pressure chemically vapor deposited boron nitride and titanium nitride films

This study has investigated the interrelationships governing the growth kinetics, resulting compositions, and properties of boron nitride (B-C-N-H) and titanium nitride (Ti-N-Cl) films synthesized by low pressure chemical vapor deposition (LPCVD) using ammonia (NH3)/triethylamine-borane and NH3/titanium tetrachloride as reactants, respectively.Several analytical methods such as the FTIR, UVNisible spectroscopy, XPS, AES, RBS, SEM, and XRD were used to study the stoichiometry and structure of the deposited films. The B-N-C-H films were synthesized over a temperature range of 300 to 8500C at various flow rate ratios of the reactants and total pressure range of 50 to 150 mTorr. The deposits were amorphous in all cases having an index of refraction ranging between 1.76 and 2.47 depending on the composition of the films. The stress of the deposited films varied from +240 to -200 Wa, depending on the deposition parameters. The hardness and Young\u27s modulus were found to be between 5 to 12 GPa and 50 to 120 GPa, respectively. Electrical properties of the BN films were measured using metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) structures. The films did not react with water vapor and exhibited dielectric constant between 3.12 and 5.5. Free standing X-ray windows with thickness varying from 2000Å to 12,000Å, were fabricated using the mildly tensile and compressive films and X-ray transmission studies through these windows indicate significantly lower absorption when compared to the commercially available polymeric X-ray windows. The Ti-N-Cl deposits exhibited an Arrhenius d ependence in the deposition temperature regime of 450 to 600 °C from which an activation energy of ~42 kJ/mol was calculated. The growth rate dependencies on the partial pressures of NH3 (50 to 100 mTorr) and TiC14 (1 to 12 mTorr) yielded reaction rate orders of 1.37 and -0.42 respectively. Films with compositions trending towards stoichiometry were produced as the deposition temperature was decreased and the NH3 partial pressure was increased. The chlorine concentration in the films was observed to decrease from ~8 % (a/o) at the deposition temperature of 450 °C down to ~0.2 % (a/o) at 850 °C. The film density values increased from 3.53 to 5.02 g/cm3 as the deposition temperature was increased from 550 to 850 °C. The resistivity of the films was dependent on changes in deposition temperature and flow rate ratios. The lowest resistivity value of 86 µΩcm was measured for a deposition temperature of 600°C and an NH3/TiCl4 flow ratio of 10/1. The film stress was found to be tensile for all deposits and to decrease with higher deposition temperatures. Nanoindentation measurements yielded values for the hardness and Young\u27s modulus of the films to be around 15 and 250 GPa, respectively. X-ray diffraction measurements revealed in all cases the presence of cubic TiN phase with a preferred (200) orientation. For the investigated aspect ratios of up to 4: 1, the deposits were observed to exhibit conformal step coverage over the investigated range of processing conditions

単結晶SiCの放電加工システムの開発

学位の種別: 課程博士審査委員会委員 : (主査)東京大学教授 国枝 正典, 東京大学教授 横井 秀俊, 東京大学教授 金 範埈, 東京大学准教授 山本 晃生, 名古屋工業大学准教授 早川 伸哉University of Tokyo(東京大学

Silicon thin films for mobile energy electronics

Consumer needs for mobile devices include the requirement for longer battery life, so that recharging can be performed less frequently or eliminated completely. To this end a key component of any mobile system is a high power and high energy density battery. An alternative to better batteries is for mobile devices to harvest some of their own energy. Solar energy is an accessible, free and environmentally friendly source of energy, making it ideal for powering mobile devices. In this work we present a low deposition temperature (150°C), thin-film solar power harvesting system. Low deposition temperature of thin film silicon and associated alloys allows for fabrication on plastic in order to realize lightweight and robust integrated systems. The system consists of a thin film transistor (TFT) circuit and thin film photovoltaic (PV) array. The circuit functions as a simple DC-DC regulator and maximum power point tracking unit (MPPT). Amorphous silicon (a-Si:H) is used as the primary thin-film material for the fabrication of the devices. One of the challenges when fabricating devices at low temperatures is the high defect density in a-Si:H due to hydrogen clustering. In here the He in addition to the SiH4 and H2 is used to minimise hydrogen clustering. Using the optimised films, TFT and PV devices are fabricated, and analysed. Low deposition temperatures influence TFT properties. Contact resistance and dynamic instability of TFTs are considered. New extraction methods and their effect on device mobility are presented. A power conditioning TFT circuit is proposed. A model is developed to analyse the circuit’s output stability as a function of stressing and light intensity. System efficiency and its dependence on circuit efficiency and solar cell utilisation are discussed. The PV array and the TFT circuit are fabricated using lithography techniques, with a maximum process temperature of 150°C. The circuit can provide a degree of output power stability over a wide range of light intensities and stressing times, making it suitable for use with SC. In this work peak system efficiency of 18% is achieved. Despite the circuit’s low efficiency, it has the advantage of fabrication on plastic substrates and better integrability within mobile devices