Representations of a class of lattice type vertex algebras

In this paper we study the representation theory for certain ``half lattice vertex algebras.'' In particular we construct a large class of irreducible modules for these vertex algebras. We also discuss how the representation theory of these vertex algebras are related to the representation theory of some associative algebras.Comment: latex 24 page

A General Framework for Sound and Complete Floyd-Hoare Logics

This paper presents an abstraction of Hoare logic to traced symmetric monoidal categories, a very general framework for the theory of systems. Our abstraction is based on a traced monoidal functor from an arbitrary traced monoidal category into the category of pre-orders and monotone relations. We give several examples of how our theory generalises usual Hoare logics (partial correctness of while programs, partial correctness of pointer programs), and provide some case studies on how it can be used to develop new Hoare logics (run-time analysis of while programs and stream circuits).Comment: 27 page

Highest weight Harish-Chandra supermodules and their geometric realizations

In this paper we discuss the highest weight $\frak k_r$-finite representations of the pair $(\frak g_r,\frak k_r)$ consisting of $\frak g_r$, a real form of a complex basic Lie superalgebra of classical type $\frak g$ (${\frak g}\neq A(n,n)$), and the maximal compact subalgebra $\frak k_r$ of $\frak g_{r,0}$, together with their geometric global realizations. These representations occur, as in the ordinary setting, in the superspaces of sections of holomorphic super vector bundles on the associated Hermitian superspaces $G_r/K_r$.Comment: This article contains of part of the material originally posted as arXiv:1503.03828 and arXiv:1511.01420. The rest of the material was posted as arXiv:1801.07181 and will also appear in an enlarged version as subsequent postin

Circuit design tool. User's manual, revision 2

The CAM chip design was produced in a UNIX software environment using a design tool that supports definition of digital electronic modules, composition of these modules into higher level circuits, and event-driven simulation of these circuits. Our design tool provides an interface whose goals include straightforward but flexible primitive module definition and circuit composition, efficient simulation, and a debugging environment that facilitates design verification and alteration. The tool provides a set of primitive modules which can be composed into higher level circuits. Each module is a C-language subroutine that uses a set of interface protocols understood by the design tool. Primitives can be altered simply by recoding their C-code image; in addition new primitives can be added allowing higher level circuits to be described in C-code rather than as a composition of primitive modules--this feature can greatly enhance the speed of simulation