Formal Foundations for the Generation of Heterogeneous Executable Specifications in SystemC from UML/MARTE Models

Medical genetic

Mastering Heterogeneous Behavioural Models

Heterogeneity is one important feature of complex systems, leading to the complexity of their construction and analysis. Moving the heterogeneity at model level helps in mastering the difficulty of composing heterogeneous models which constitute a large system. We propose a method made of an algebra and structure morphisms to deal with the interaction of behavioural models, provided that they are compatible. We prove that heterogeneous models can interact in a safe way, and therefore complex heterogeneous systems can be built and analysed incrementally. The Uppaal tool is targeted for experimentations.Comment: 16 pages, a short version to appear in MEDI'201

SystemC^FL : a formalism for hardware/software co-design

SystemCFL is a formal language for hardware/software codesign. Principally, SystemCFL is the formalization of SyslemC based on classical process algebra ACP. The language is aimed to give formal specification of SystemC designs and perform formal analysis of SystemC processes. This paper, designed for the first-time user of SystemCFL, guides the reader through modeling, analyzing and verifying designs using SystemCFL. This paper illustrates the use of SysternCFL with two case studies taken from literature

Extensions of SystemC^FL for mixed-signal systems and formal verification

The formal language SystemC^FL is the formalization of SystemC. The language semantics of SystemC^FL was formally defined in a standard structured operational semantics (SOS) style. In this paper, we first provide an overview of the current status of the formal language SystemC^FL and show some practical applications of SystemC^FL.Then, we give an outline for the latest developments of SystemC^FL. These developments include extensions of SystemC^FL for modeling mixed-signal systems and formal verification

Reusing RTL assertion checkers for verification of SystemC TLM models

The recent trend towards system-level design gives rise to new challenges for reusing existing RTL intellectual properties (IPs) and their verification environment in TLM. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still under-explored, particularly when ABV is adopted. Some frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet, except by using transactors to create a mixed simulation between the TLM design and the RTL checkers corresponding to the assertions. However, the use of transactors may lead to longer verification time due to the need of developing and verifying the transactors themselves. Moreover, the simulation time is negatively affected by the presence of transactors, which slow down the simulation at the speed of the slowest parts (i.e., RTL checkers). This article proposes an alternative methodology that does not require transactors for reusing assertions, originally defined for a given RTL IP, in order to verify the corresponding TLM model. Experimental results have been conducted on benchmarks with different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

A Language and Toolset for the Synthesis and Efficient Simulation of Clock-Cycle-True Signal-Processing Algorithms

Optimal simulation speed and synthesizability are contradictory requirements for a hardware description language. This paper presents a language and toolset that enables both synthesis and fast simulation of fixed-point signal processing algorithms at the register-transfer level using a single system description. This is achieved by separate code generators for different purposes. Code-generators have been developed for fast simulation (using ANSI-C) and for synthesis (using VHDL). The simulation performance of the proposed approach has been compared with other known methods and turns out to be comparable in speed to the fastest among them

On the Reuse of RTL assertions in Systemc TLM Verification

Reuse of existing and already verified intellectual property (IP) models is a key strategy to cope with the com- plexity of designing modern system-on-chips (SoC)s under ever stringent time-to-market requirements. In particular, the recent trend towards system-level design and transaction level modeling (TLM) gives rise to new challenges for reusing existing RTL IPs and their verification environment in TLM-based design flows. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still underexplored, particularly when assertion-based verification (ABV) is adopted. Some techniques and frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet. This paper proposes a methodology to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. Experimental results have been conducted on benchmarks of different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

DesyreML: a SysML profile for heterogeneous embedded systems

International audienceWe propose a novel language for the formal description of heterogeneous embedded systems (DesyreML). As the main contribution, the language is formally described in terms of semantics and concrete syntax based on the SysML language. We define the concept of thick connector to allow for heterogeneous components communication and computation for multiple semantic domains (synchronous reactive, continuous time, discrete time, discrete-event). As technological application, a verification flow based on model-transformation techniques is described showing the use of an enriched version of the SystemC-AMS simulation kernel that is capable of simulating heterogeneous systems containing combinatorial loops. Finally, the language and the analysis flow are applied to a cruise control case study